Thomas L. Jeremiah

Person

Hillsborough, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Load request scheduling in a cache hierarchy
- Patent number 8,521,982
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Robert A. Cargnoni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache replacement
- Patent number 8,347,037
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Guy L. Guthrie
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Victim cache replacement
- Patent number 8,327,072
- Issue date Dec 4, 2012
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Empirically based dynamic control of acceptance of victim cache lat...
- Patent number 8,327,073
- Issue date Dec 4, 2012
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chaining multiple smaller store queue entries for more efficient st...
- Patent number 8,166,246
- Issue date Apr 24, 2012
- International Business Machines Corporation
- Guy Lynn Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache line selection
- Patent number 8,117,397
- Issue date Feb 14, 2012
- International Business Machines Corporation
- Guy L. Guthrie
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Distributed address arbitration scheme for symmetrical multiprocess...
- Patent number 7,484,052
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Brian M. Bass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch target cache and method for efficiently obtaining target pat...
- Patent number 6,829,702
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Thomas Leo Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache address generation with and without carry-in
- Patent number 5,940,877
- Issue date Aug 17, 1999
- International Business Machines Corporation
- Richard James Eickemeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiway associative external microprocessor cache
- Patent number 5,909,694
- Issue date Jun 1, 1999
- International Business Machines Corporation
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-cache-line compounding algorithm for scism processors
- Patent number 5,701,430
- Issue date Dec 23, 1997
- International Business Machines Corporation
- Thomas Leo Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for executing scalar instructions in parallel based on contr...
- Patent number 5,504,932
- Issue date Apr 2, 1996
- International Business Machines Corporation
- Stamatis Vassiliadis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-cache-line compounding algorithm for scism processors
- Patent number 5,446,850
- Issue date Aug 29, 1995
- International Business Machines Corporation
- Thomas L. Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microcode generation for a scalable compound instruction set machine
- Patent number 5,398,321
- Issue date Mar 14, 1995
- International Business Machines Corporation
- Thomas L. Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system accelerator for multi-word cross-boundary storage a...
- Patent number 5,386,531
- Issue date Jan 31, 1995
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for issuing instructions for parallel execution subsequent t...
- Patent number 5,303,356
- Issue date Apr 12, 1994
- International Business Machines Corporation
- Stamatis Vassiliadis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline for removing and concurrently executing two or more branch...
- Patent number 5,287,467
- Issue date Feb 15, 1994
- International Business Machines Corporation
- Bartholomew Blaner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calculating AC chip performance using the LSSD scan path
- Patent number 5,039,939
- Issue date Aug 13, 1991
- International Business Machines Corporation
- Carroll J. Dick
- G01 - MEASURING TESTING
Information Patent Grant
Interruptible cache loading to assure immediate data access from cache
- Patent number 4,964,041
- Issue date Oct 16, 1990
- IBM Corporation
- Thomas L. Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity for computer system having an array of external registers
- Patent number 4,234,955
- Issue date Nov 18, 1980
- International Business Machines Corporation
- Thomas L. Jeremiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Oversized data detection hardware for data processors which store d...
- Patent number 4,021,655
- Issue date May 3, 1977
- International Business Machines Corporation
- Robert Albert Healey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Empirically Based Dynamic Control of Acceptance of Victim Cache Lat...
- Publication number 20100262784
- Publication date Oct 14, 2010
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Victim Cache Line Selection
- Publication number 20100153650
- Publication date Jun 17, 2010
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Victim Cache Replacement
- Publication number 20100100682
- Publication date Apr 22, 2010
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Victim Cache Replacement
- Publication number 20100023695
- Publication date Jan 28, 2010
- International Business Machines Corporation
- Guy L. Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE E...
- Publication number 20090198867
- Publication date Aug 6, 2009
- Guy Lynn Guthrie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed address arbitration scheme for symmetrical multiprocess...
- Publication number 20060253661
- Publication date Nov 9, 2006
- International Business Machines Corporation
- Brian M. Bass
- G06 - COMPUTING CALCULATING COUNTING

Thomas L. Jeremiah

Person

Patents Grantslast 30 patents

Load request scheduling in a cache hierarchy

Victim cache replacement

Victim cache replacement

Empirically based dynamic control of acceptance of victim cache lat...

Chaining multiple smaller store queue entries for more efficient st...

Victim cache line selection

Distributed address arbitration scheme for symmetrical multiprocess...

Branch target cache and method for efficiently obtaining target pat...

Cache address generation with and without carry-in

Multiway associative external microprocessor cache

Cross-cache-line compounding algorithm for scism processors

System for executing scalar instructions in parallel based on contr...

Cross-cache-line compounding algorithm for scism processors

Microcode generation for a scalable compound instruction set machine

Computer system accelerator for multi-word cross-boundary storage a...

System for issuing instructions for parallel execution subsequent t...

Pipeline for removing and concurrently executing two or more branch...

Calculating AC chip performance using the LSSD scan path

Interruptible cache loading to assure immediate data access from cache

Parity for computer system having an array of external registers

Oversized data detection hardware for data processors which store d...

Patents Applicationslast 30 patents

Empirically Based Dynamic Control of Acceptance of Victim Cache Lat...

Victim Cache Line Selection

Victim Cache Replacement

Victim Cache Replacement

METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE E...

Distributed address arbitration scheme for symmetrical multiprocess...