Thomas M. Maffitt

Person

Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 11,152,063
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,998,045
- Issue date May 4, 2021
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,943,658
- Issue date Mar 9, 2021
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,937,496
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,762,959
- Issue date Sep 1, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM sense amplifier with second stage offset cancellation
- Patent number 10,726,898
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Thomas Martin Maffitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Trimming MRAM sense amp with offset cancellation
- Patent number 10,726,897
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Thomas Martin Maffitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,692,576
- Issue date Jun 23, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
High gain sense amplifier with offset cancellation for magnetoresis...
- Patent number 10,658,022
- Issue date May 19, 2020
- International Business Machines Corporation
- Thomas Martin Maffitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,566,057
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,535,403
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 10,424,375
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory with an incrementally ramped write-reference vo...
- Patent number 10,037,802
- Issue date Jul 31, 2018
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory using a write refe...
- Patent number 9,911,492
- Issue date Mar 6, 2018
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Content-addressable memory having multiple reference matchlines to...
- Patent number 9,704,575
- Issue date Jul 11, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
TCAM structures with reduced power supply noise
- Patent number 9,601,200
- Issue date Mar 21, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Matchline precharge architecture for self-reference matchline sensing
- Patent number 9,583,192
- Issue date Feb 28, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory
- Patent number 9,502,107
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Offset-cancelling self-reference STT-MRAM sense amplifier
- Patent number 9,384,792
- Issue date Jul 5, 2016
- GLOBALFOUNDRIES Inc.
- Anthony R. Bonaccio
- G11 - INFORMATION STORAGE
Information Patent Grant
Writing multiple levels in a phase change memory using a write/read...
- Patent number 9,299,431
- Issue date Mar 29, 2016
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory cycle timer and method
- Patent number 8,520,458
- Issue date Aug 27, 2013
- International Business Machines Corporation
- John A. Gabric
- G11 - INFORMATION STORAGE
Information Patent Grant
Non volatile cell and architecture with single bit random access re...
- Patent number 8,345,475
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump system and method utilizing adjustable output charge an...
- Patent number 8,300,489
- Issue date Oct 30, 2012
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory cycle timer and method
- Patent number 8,233,345
- Issue date Jul 31, 2012
- International Business Machines Corporation
- John A Gabric
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method using distributed phase change elements for acro...
- Patent number 7,882,455
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Nazmul Habib
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for implementing concurrent multiple level sen...
- Patent number 7,778,065
- Issue date Aug 17, 2010
- International Business Machines Corporation
- Mark C. H. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing self-referencing read operati...
- Patent number 7,660,152
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Mark C. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing precise sensing of PCRAM devices
- Patent number 7,535,783
- Issue date May 19, 2009
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Precharging the write path of an MRAM device for fast write operation
- Patent number 7,057,924
- Issue date Jun 6, 2006
- Infineon Technologies AG
- Stefan Lammers
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline on and off voltage compensation circuit based on the array...
- Patent number 6,693,843
- Issue date Feb 17, 2004
- Infineon Technologies AG
- Thomas M. Maffitt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20200075096
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20200075097
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20190355417
- Publication date Nov 21, 2019
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20190355416
- Publication date Nov 21, 2019
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20190267086
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20190267087
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20180277209
- Publication date Sep 27, 2018
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20180277210
- Publication date Sep 27, 2018
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20180068725
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO...
- Publication number 20170200500
- Publication date Jul 13, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20170004884
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE
- Publication number 20160365146
- Publication date Dec 15, 2016
- International Business Machines Corporation
- Igor ARSOVSKI
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20150364195
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20150364194
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Chung H. LAM
- G11 - INFORMATION STORAGE
Information Patent Application
Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier
- Publication number 20150294706
- Publication date Oct 15, 2015
- International Business Machines Corporation
- Anthony R. Bonaccio
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY
- Publication number 20150206582
- Publication date Jul 23, 2015
- International Business Machines Corporation
- Chung H. LAM
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE MEMORY CYCLE TIMER AND METHOD
- Publication number 20120266115
- Publication date Oct 18, 2012
- International Business Machines Corporation
- John A. GABRIC
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE CHANGE MEMORY CYCLE TIMER AND METHOD
- Publication number 20120057401
- Publication date Mar 8, 2012
- International Business Machines Corporation
- John A. GABRIC
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE PUMP SYSTEM AND METHOD UTILIZING ADJUSTABLE OUTPUT CHARGE AN...
- Publication number 20110170368
- Publication date Jul 14, 2011
- International Business Machines Corporation
- John A. FIFIELD
- G11 - INFORMATION STORAGE
Information Patent Application
NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS RE...
- Publication number 20110116312
- Publication date May 19, 2011
- International Business Machines Corporation
- Chung H. Lam
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit And Method Using Distributed Phase Change Elements For Acro...
- Publication number 20090282375
- Publication date Nov 12, 2009
- Nazmul Habib
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATI...
- Publication number 20090273968
- Publication date Nov 5, 2009
- Mark C. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SEN...
- Publication number 20090219749
- Publication date Sep 3, 2009
- Mark C. H. Lamorey
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES
- Publication number 20090086534
- Publication date Apr 2, 2009
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Precharging the write path of an MRAM device for fast write operation
- Publication number 20050157546
- Publication date Jul 21, 2005
- Stefan Lammers
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM word line voltage control to insure full cell writeback level
- Publication number 20020159301
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Wayne F. Ellis
- G11 - INFORMATION STORAGE
Information Patent Application
Oxide tracking voltage reference
- Publication number 20020130672
- Publication date Sep 19, 2002
- International Business Machines Corporation
- John Atkinson Fifield
- G01 - MEASURING TESTING

Thomas M. Maffitt

Person

Patents Grantslast 30 patents

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

MRAM sense amplifier with second stage offset cancellation

Trimming MRAM sense amp with offset cancellation

Writing multiple levels in a phase change memory

High gain sense amplifier with offset cancellation for magnetoresis...

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Writing multiple levels in a phase change memory

Phase change memory with an incrementally ramped write-reference vo...

Writing multiple levels in a phase change memory using a write refe...

Content-addressable memory having multiple reference matchlines to...

TCAM structures with reduced power supply noise

Matchline precharge architecture for self-reference matchline sensing

Writing multiple levels in a phase change memory

Offset-cancelling self-reference STT-MRAM sense amplifier

Writing multiple levels in a phase change memory using a write/read...

Phase change memory cycle timer and method

Non volatile cell and architecture with single bit random access re...

Charge pump system and method utilizing adjustable output charge an...

Phase change memory cycle timer and method

Circuit and method using distributed phase change elements for acro...

Method and apparatus for implementing concurrent multiple level sen...

Method and apparatus for implementing self-referencing read operati...

Apparatus and method for implementing precise sensing of PCRAM devices

Precharging the write path of an MRAM device for fast write operation

Wordline on and off voltage compensation circuit based on the array...

Patents Applicationslast 30 patents

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO...

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier

WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY

PHASE CHANGE MEMORY CYCLE TIMER AND METHOD

PHASE CHANGE MEMORY CYCLE TIMER AND METHOD

CHARGE PUMP SYSTEM AND METHOD UTILIZING ADJUSTABLE OUTPUT CHARGE AN...

NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS RE...

Circuit And Method Using Distributed Phase Change Elements For Acro...

METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATI...

METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SEN...

APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES

Precharging the write path of an MRAM device for fast write operation

DRAM word line voltage control to insure full cell writeback level

Oxide tracking voltage reference