Thomas Michael Wolf

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Orlando, FL, US

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Patents Grantslast 30 patents

Information Patent Grant
Define via in dual damascene process
- Patent number 7,160,799
- Issue date Jan 9, 2007
- Agere Systems Inc.
- Steven Alan Lytle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for avoiding notching in a semiconductor interconnect during...
- Patent number 6,559,062
- Issue date May 6, 2003
- Agere Systems, INC
- Stephen Ward Downey
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Define via in dual damascene process
- Publication number 20050067710
- Publication date Mar 31, 2005
- Steven Alan Lytle
- H01 - BASIC ELECTRIC ELEMENTS