Thomas R. Wik

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-cost efficient solar panels
- Patent number 9,780,722
- Issue date Oct 3, 2017
- Thomas Robert Wik
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Error detection and correction in ternary content addressable memor...
- Patent number 9,762,261
- Issue date Sep 12, 2017
- eSilicon Corporation
- Michael Anthony Zampaglione
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error detection and correction in binary content addressable memory...
- Patent number 9,529,669
- Issue date Dec 27, 2016
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-cost solar collector
- Patent number 8,921,680
- Issue date Dec 30, 2014
- Thomas Robert Wik
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Resonant digital data transmission
- Patent number 7,746,921
- Issue date Jun 29, 2010
- Thomas Robert Wik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Crossbar switch with grouped inputs and outputs
- Patent number 7,603,509
- Issue date Oct 13, 2009
- Adaptive Design Solutions, Inc.
- Thomas Robert Wik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditioning logic technology
- Patent number 7,557,618
- Issue date Jul 7, 2009
- Thomas R. Wik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit memory having column redundancy
- Patent number 6,507,524
- Issue date Jan 14, 2003
- LSI Logic Corporation
- Ghasi Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Way to compensate the effect of coupling between bitlines in a mult...
- Patent number 6,370,078
- Issue date Apr 9, 2002
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-port semiconductor memory and compiler having capacitance com...
- Patent number 6,233,197
- Issue date May 15, 2001
- LSI Logic Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system using multiple storage mechanisms to enable storage a...
- Patent number 6,137,716
- Issue date Oct 24, 2000
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system which permits logic signal routing over on-chip m...
- Patent number 6,018,480
- Issue date Jan 25, 2000
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing memory operations employing self-repair circuitry...
- Patent number 5,987,632
- Issue date Nov 16, 1999
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell capable of storing more than two logic states by using...
- Patent number 5,982,659
- Issue date Nov 9, 1999
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing memory refresh operations wherein subthreshold le...
- Patent number 5,903,505
- Issue date May 11, 1999
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and method for multivalued logic storage by process...
- Patent number 5,867,423
- Issue date Feb 2, 1999
- LSI Logic Corporation
- Ashok Kapoor
- G11 - INFORMATION STORAGE
Information Patent Grant
Ram cell capable of storing 3 logic states
- Patent number 5,847,990
- Issue date Dec 8, 1998
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system using multiple storage mechanisms to enable storage a...
- Patent number 5,841,695
- Issue date Nov 24, 1998
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system which enables storage and retrieval of more than two...
- Patent number 5,808,932
- Issue date Sep 15, 1998
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit including write control unit wherein subthreshold le...
- Patent number 5,796,650
- Issue date Aug 18, 1998
- LSI Logic Corporation
- Thomas R. Wik
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including an on-chip temperature sensor for regulatin...
- Patent number 5,784,328
- Issue date Jul 21, 1998
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell capable of storing more than two logic states by using...
- Patent number 5,761,110
- Issue date Jun 2, 1998
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Error Detection and Correction in Binary Content Addressable Memory...
- Publication number 20150095740
- Publication date Apr 2, 2015
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Detection and Correction in Ternary Content Addressable Memor...
- Publication number 20150095738
- Publication date Apr 2, 2015
- eSilicon Corporation
- Michael Anthony Zampaglione
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit margin stress test system
- Publication number 20060218455
- Publication date Sep 28, 2006
- Silicon Design Solution, Inc.
- Kevin Robert LeClair
- G01 - MEASURING TESTING

Thomas R. Wik

Person

Patents Grantslast 30 patents

Low-cost efficient solar panels

Error detection and correction in ternary content addressable memor...

Error detection and correction in binary content addressable memory...

Low-cost solar collector

Resonant digital data transmission

Crossbar switch with grouped inputs and outputs

Conditioning logic technology

Integrated circuit memory having column redundancy

Way to compensate the effect of coupling between bitlines in a mult...

Multi-port semiconductor memory and compiler having capacitance com...

Memory system using multiple storage mechanisms to enable storage a...

Method and system which permits logic signal routing over on-chip m...

Method of testing memory operations employing self-repair circuitry...

Memory cell capable of storing more than two logic states by using...

Method of testing memory refresh operations wherein subthreshold le...

Memory circuit and method for multivalued logic storage by process...

Ram cell capable of storing 3 logic states

Memory system using multiple storage mechanisms to enable storage a...

Memory system which enables storage and retrieval of more than two...

Memory circuit including write control unit wherein subthreshold le...

Memory system including an on-chip temperature sensor for regulatin...

Memory cell capable of storing more than two logic states by using...

Patents Applicationslast 30 patents

Error Detection and Correction in Binary Content Addressable Memory...

Error Detection and Correction in Ternary Content Addressable Memor...

Integrated circuit margin stress test system