Thomas Roehr

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Write circuit, non-volatile data storage, method for writing to a p...
- Patent number 11,495,273
- Issue date Nov 8, 2022
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with memory cells having changeable resistance and...
- Patent number 7,737,428
- Issue date Jun 15, 2010
- Qimonda AG
- Ralf Symanczyk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device including electrical circuit configured to provide re...
- Patent number 7,715,226
- Issue date May 11, 2010
- Qimonda AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory arrangement
- Patent number 7,561,460
- Issue date Jul 14, 2009
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with resistance memory cell and evaluation circuit
- Patent number 7,499,349
- Issue date Mar 3, 2009
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell for storage of a data item in an integrate...
- Patent number 7,495,945
- Issue date Feb 24, 2009
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Switching device for configurable interconnect and method for prepa...
- Patent number 7,414,257
- Issue date Aug 19, 2008
- Infineon Technologies AG
- Thomas D. Happ
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory having CBRAM memory cells and method
- Patent number 7,372,716
- Issue date May 13, 2008
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit and method for reading from resistance memory cells
- Patent number 7,355,898
- Issue date Apr 8, 2008
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including electrical circuit configured to provide re...
- Patent number 7,327,603
- Issue date Feb 5, 2008
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device with a memory cell
- Patent number 7,289,350
- Issue date Oct 30, 2007
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for writing data into a memory cell of a conductive bridging...
- Patent number 7,257,013
- Issue date Aug 14, 2007
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit having memory cells which have a resistance memory e...
- Patent number 7,251,152
- Issue date Jul 31, 2007
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory arrangement
- Patent number 7,215,568
- Issue date May 8, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming multi-bit charge-trapping memory cell arrays
- Patent number 7,184,317
- Issue date Feb 27, 2007
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory
- Patent number 7,092,304
- Issue date Aug 15, 2006
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Switching device for reconfigurable interconnect and method for mak...
- Patent number 6,972,427
- Issue date Dec 6, 2005
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Imprint suppression circuit scheme
- Patent number 6,950,328
- Issue date Sep 27, 2005
- Infineon Technologies AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for preventing unwanted programming in an MRAM configuration
- Patent number 6,577,527
- Issue date Jun 10, 2003
- Infineon Technologies AG
- Martin Freitag
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic driver circuit for word lines in a memory matrix, and me...
- Patent number 6,501,686
- Issue date Dec 31, 2002
- Infineon Technologies AG
- Thomas Boehm
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating a ferroelectric memory configuration
- Patent number 6,500,677
- Issue date Dec 31, 2002
- Infineon Technologies AG
- Renate Bergmann
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WRITE CIRCUIT, NON-VOLATILE DATA STORAGE, METHOD FOR WRITING TO A P...
- Publication number 20210272610
- Publication date Sep 2, 2021
- INFINEON TECHNOLOGIES AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING CIRCUITRY TO PERFORM WRITE AND ERASE O...
- Publication number 20080123400
- Publication date May 29, 2008
- INFINEON TECHNOLOGIES AG
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Memory Arrangement
- Publication number 20070211515
- Publication date Sep 13, 2007
- Infineon Technologies AG
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH RESISTANCE MEMORY CELL AND EVALUATION CIRCUIT
- Publication number 20070147102
- Publication date Jun 28, 2007
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Method for writing data into a memory cell of a conductive bridging...
- Publication number 20070058417
- Publication date Mar 15, 2007
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Electrical circuit and a method for operating a programmable metall...
- Publication number 20070041251
- Publication date Feb 22, 2007
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS
- Publication number 20070002645
- Publication date Jan 4, 2007
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Electronic device with a memory cell
- Publication number 20060221663
- Publication date Oct 5, 2006
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile memory cell for storage of a data item in an integrate...
- Publication number 20060181916
- Publication date Aug 17, 2006
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Arrangement and method for reading from resistance memory cells
- Publication number 20060067147
- Publication date Mar 30, 2006
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
CBRAM memory cell arrangement and method for programming CBRAM memo...
- Publication number 20060062043
- Publication date Mar 23, 2006
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Memory component with memory cells having changeable resistance and...
- Publication number 20060060832
- Publication date Mar 23, 2006
- Ralf Symanczyk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Resistive memory arrangement
- Publication number 20060050547
- Publication date Mar 9, 2006
- Corvin Liaw
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit having memory cells which have a resistance memory e...
- Publication number 20060050546
- Publication date Mar 9, 2006
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory
- Publication number 20050276140
- Publication date Dec 15, 2005
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
SWITCHING DEVICE FOR RECONFIGURABLE INTERCONNECT AND METHOD FOR MAK...
- Publication number 20050242337
- Publication date Nov 3, 2005
- Thomas Roehr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Switching device for configurable interconnect and method for prepa...
- Publication number 20050219800
- Publication date Oct 6, 2005
- Thomas D. Happ
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Imprint suppression circuit scheme
- Publication number 20050128779
- Publication date Jun 16, 2005
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Method for fabricating a ferroelectric memory configuration
- Publication number 20020110935
- Publication date Aug 15, 2002
- Renate Bergmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for preventing unwanted programming in an MRAM configuration
- Publication number 20020085411
- Publication date Jul 4, 2002
- Martin Freitag
- B82 - NANO-TECHNOLOGY
Information Patent Application
Electronic driver circuit for word lines in a memory matrix, and me...
- Publication number 20020050448
- Publication date May 2, 2002
- Thomas Boehm
- G11 - INFORMATION STORAGE

Thomas Roehr

Person

Patents Grantslast 30 patents

Write circuit, non-volatile data storage, method for writing to a p...

Memory component with memory cells having changeable resistance and...

Memory device including electrical circuit configured to provide re...

Resistive memory arrangement

Memory with resistance memory cell and evaluation circuit

Non-volatile memory cell for storage of a data item in an integrate...

Switching device for configurable interconnect and method for prepa...

Memory having CBRAM memory cells and method

Integrated circuit and method for reading from resistance memory cells

Memory device including electrical circuit configured to provide re...

Electronic device with a memory cell

Method for writing data into a memory cell of a conductive bridging...

Memory circuit having memory cells which have a resistance memory e...

Resistive memory arrangement

Method for programming multi-bit charge-trapping memory cell arrays

Semiconductor memory

Switching device for reconfigurable interconnect and method for mak...

Imprint suppression circuit scheme

Method for preventing unwanted programming in an MRAM configuration

Electronic driver circuit for word lines in a memory matrix, and me...

Method for fabricating a ferroelectric memory configuration

Patents Applicationslast 30 patents

WRITE CIRCUIT, NON-VOLATILE DATA STORAGE, METHOD FOR WRITING TO A P...

INTEGRATED CIRCUIT INCLUDING CIRCUITRY TO PERFORM WRITE AND ERASE O...

Resistive Memory Arrangement

MEMORY WITH RESISTANCE MEMORY CELL AND EVALUATION CIRCUIT

Method for writing data into a memory cell of a conductive bridging...

Electrical circuit and a method for operating a programmable metall...

METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS

Electronic device with a memory cell

Non-volatile memory cell for storage of a data item in an integrate...

Arrangement and method for reading from resistance memory cells

CBRAM memory cell arrangement and method for programming CBRAM memo...

Memory component with memory cells having changeable resistance and...

Resistive memory arrangement

Memory circuit having memory cells which have a resistance memory e...

Semiconductor memory

SWITCHING DEVICE FOR RECONFIGURABLE INTERCONNECT AND METHOD FOR MAK...

Switching device for configurable interconnect and method for prepa...

Imprint suppression circuit scheme

Method for fabricating a ferroelectric memory configuration

Method for preventing unwanted programming in an MRAM configuration

Electronic driver circuit for word lines in a memory matrix, and me...