Thomas Vogelsang

Person

Jericho, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked DRAM device and method of manufacture
- Patent number 12,170,126
- Issue date Dec 17, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Grant
Block copy
- Patent number 12,086,441
- Issue date Sep 10, 2024
- RAMBUS INC.
- Michael Raymond Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage and access of data and tags in a multi-way set associative...
- Patent number 12,072,807
- Issue date Aug 27, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple precision memory system
- Patent number 12,026,104
- Issue date Jul 2, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having non-uniform refresh
- Patent number 12,020,740
- Issue date Jun 25, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-modal refresh of dynamic, random-access memory
- Patent number 12,001,697
- Issue date Jun 4, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with persistent calibration
- Patent number 11,989,430
- Issue date May 21, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-reduced DRAM stack
- Patent number 11,972,121
- Issue date Apr 30, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having hidden refresh
- Patent number 11,934,654
- Issue date Mar 19, 2024
- RAMBUS INC.
- Michael Raymond Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked device communication
- Patent number 11,922,066
- Issue date Mar 5, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2T-1R architecture for resistive ram
- Patent number 11,908,515
- Issue date Feb 20, 2024
- Hefei Reliance Memory Limited
- Deepak Chandra Sekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked DRAM device and method of manufacture
- Patent number 11,894,093
- Issue date Feb 6, 2024
- RAMBUS INC.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial array refresh timing
- Patent number 11,868,619
- Issue date Jan 9, 2024
- RAMBUS INC.
- Liji Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System application of DRAM component with cache mode
- Patent number 11,842,762
- Issue date Dec 12, 2023
- RAMBUS INC.
- Frederick Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with multiple open rows per bank
- Patent number 11,842,761
- Issue date Dec 12, 2023
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component having internal read-modify-write operation
- Patent number 11,822,822
- Issue date Nov 21, 2023
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dram device with multiple voltage domains
- Patent number 11,823,734
- Issue date Nov 21, 2023
- RAMBUS INC.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with deferred fractional row activation
- Patent number 11,804,250
- Issue date Oct 31, 2023
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with efficient write operations
- Patent number 11,790,973
- Issue date Oct 17, 2023
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked memory device with paired channels
- Patent number 11,775,213
- Issue date Oct 3, 2023
- RAMBUS INC.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory subsystem for a cryogenic digital system
- Patent number 11,653,476
- Issue date May 16, 2023
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM retention test method for dynamic error correction
- Patent number 11,646,090
- Issue date May 9, 2023
- RAMBUS INC.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic processing speed
- Patent number 11,645,212
- Issue date May 9, 2023
- RAMBUS INC.
- Steven C. Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing through-silicon-vias
- Patent number 11,600,349
- Issue date Mar 7, 2023
- RAMBUS INC.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Grant
2T-1R architecture for resistive RAM
- Patent number 11,568,929
- Issue date Jan 31, 2023
- Hefei Reliance Memory Limited
- Deepak Chandra Sekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component having internal read-modify-write operation
- Patent number 11,347,441
- Issue date May 31, 2022
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute accelerator with 3D data flows
- Patent number 11,341,086
- Issue date May 24, 2022
- RAMBUS INC.
- Amogh Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fractional-readout oversampled image sensor
- Patent number 11,284,034
- Issue date Mar 22, 2022
- RAMBUS INC.
- Jay Endsley
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Deferred fractional memory row activation
- Patent number 11,270,741
- Issue date Mar 8, 2022
- RAMBUS INC.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced transport energy in a memory system
- Patent number 11,257,539
- Issue date Feb 22, 2022
- RAMBUS INC.
- Frederick A. Ware
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE HAVING NON-UNIFORM REFRESH
- Publication number 20240404575
- Publication date Dec 5, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE PRECISION MEMORY SYSTEM
- Publication number 20240385974
- Publication date Nov 21, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSE AMPLIFIER FOR ACTIVE STANDBY OPERATION
- Publication number 20240371432
- Publication date Nov 7, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Modal Refresh of Dynamic, Random-Access Memory
- Publication number 20240354014
- Publication date Oct 24, 2024
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH D...
- Publication number 20240345735
- Publication date Oct 17, 2024
- Rambus Inc.
- Brent Steven Haukness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE WITH PERSISTENT CALIBRATION
- Publication number 20240345745
- Publication date Oct 17, 2024
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD-REDUCED DRAM STACK
- Publication number 20240302977
- Publication date Sep 12, 2024
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE HAVING HIDDEN REFRESH
- Publication number 20240295961
- Publication date Sep 5, 2024
- Rambus Inc.
- Michael Raymond MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH IN...
- Publication number 20240281154
- Publication date Aug 22, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH CONFIGURABLE WORDLINE AND...
- Publication number 20240257860
- Publication date Aug 1, 2024
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED DEVICE COMMUNICATION
- Publication number 20240241670
- Publication date Jul 18, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED DRAM DEVICE AND METHOD OF MANUFACTURE
- Publication number 20240242741
- Publication date Jul 18, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
BOOSTED WRITEBACK VOLTAGE
- Publication number 20240203474
- Publication date Jun 20, 2024
- RAMBUS INC.
- Thomas VOGELSANG
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH VARIABLE BURST LENGTHS
- Publication number 20240177794
- Publication date May 30, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL ARRAY REFRESH TIMING
- Publication number 20240176497
- Publication date May 30, 2024
- Rambus Inc.
- Liji GOPALAKRISHNAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE
- Publication number 20240153548
- Publication date May 9, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF COMPRESSION ALGORITHMS WITH ERROR CORRECTION CODES
- Publication number 20240146336
- Publication date May 2, 2024
- Rambus Inc.
- Thomas Vogelsang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULE AUTHENTICATION
- Publication number 20240146546
- Publication date May 2, 2024
- Rambus Inc.
- Scott C. BEST
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING
- Publication number 20240127903
- Publication date Apr 18, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PER BANK
- Publication number 20240127882
- Publication date Apr 18, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS
- Publication number 20240119995
- Publication date Apr 11, 2024
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION
- Publication number 20240118837
- Publication date Apr 11, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked Memory Device with Paired Channels
- Publication number 20240086112
- Publication date Mar 14, 2024
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
- Publication number 20240062788
- Publication date Feb 22, 2024
- Rambus Inc.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
ROW HAMMER MITIGATION
- Publication number 20230395118
- Publication date Dec 7, 2023
- Rambus Inc.
- Thomas VOGELSANG
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
- Publication number 20230377668
- Publication date Nov 23, 2023
- Rambus Inc.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Circuits for Aggregating Processing Units and Dynamical...
- Publication number 20230342310
- Publication date Oct 26, 2023
- Rambus Inc.
- Steven C. Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked-Die Neural Network with Integrated High-Bandwidth Memory
- Publication number 20230153587
- Publication date May 18, 2023
- Rambus Inc.
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
2T-1R ARCHITECTURE FOR RESISTIVE RAM
- Publication number 20230154531
- Publication date May 18, 2023
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
- G11 - INFORMATION STORAGE
Information Patent Application
BUS DISTRIBUTION USING MULTIWAVELENGTH MULTIPLEXING
- Publication number 20230125262
- Publication date Apr 27, 2023
- Rambus Inc.
- Mark D. KELLAM
- G02 - OPTICS

Thomas Vogelsang

Person

Patents Grantslast 30 patents

Stacked DRAM device and method of manufacture

Block copy

Storage and access of data and tags in a multi-way set associative...

Multiple precision memory system

Memory device having non-uniform refresh

Multi-modal refresh of dynamic, random-access memory

Memory module with persistent calibration

Load-reduced DRAM stack

Memory device having hidden refresh

Stacked device communication

2T-1R architecture for resistive ram

Stacked DRAM device and method of manufacture

Partial array refresh timing

System application of DRAM component with cache mode

Memory system with multiple open rows per bank

Memory component having internal read-modify-write operation

Dram device with multiple voltage domains

Memory with deferred fractional row activation

Memory component with efficient write operations

Stacked memory device with paired channels

Memory subsystem for a cryogenic digital system

DRAM retention test method for dynamic error correction

Dynamic processing speed

Testing through-silicon-vias

2T-1R architecture for resistive RAM

Memory component having internal read-modify-write operation

Compute accelerator with 3D data flows

Fractional-readout oversampled image sensor

Deferred fractional memory row activation

Reduced transport energy in a memory system

Patents Applicationslast 30 patents

MEMORY DEVICE HAVING NON-UNIFORM REFRESH

MULTIPLE PRECISION MEMORY SYSTEM

SENSE AMPLIFIER FOR ACTIVE STANDBY OPERATION

Multi-Modal Refresh of Dynamic, Random-Access Memory

LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH D...

MEMORY MODULE WITH PERSISTENT CALIBRATION

LOAD-REDUCED DRAM STACK

MEMORY DEVICE HAVING HIDDEN REFRESH

DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH IN...

DYNAMIC RANDOM ACCESS MEMORY (DRAM) WITH CONFIGURABLE WORDLINE AND...

STACKED DEVICE COMMUNICATION

STACKED DRAM DEVICE AND METHOD OF MANUFACTURE

BOOSTED WRITEBACK VOLTAGE

DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH VARIABLE BURST LENGTHS

PARTIAL ARRAY REFRESH TIMING

SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE

INTEGRATION OF COMPRESSION ALGORITHMS WITH ERROR CORRECTION CODES

MODULE AUTHENTICATION

DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING

MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PER BANK

DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS

MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION

Stacked Memory Device with Paired Channels

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

ROW HAMMER MITIGATION

DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION

Methods and Circuits for Aggregating Processing Units and Dynamical...

Stacked-Die Neural Network with Integrated High-Bandwidth Memory

2T-1R ARCHITECTURE FOR RESISTIVE RAM

BUS DISTRIBUTION USING MULTIWAVELENGTH MULTIPLEXING