Thomas Warren Lassiter

Person

Garland, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a semiconductor device
- Patent number 10,319,899
- Issue date Jun 11, 2019
- Texas Instruments Incorporated
- Neng Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-temperature isotropic plasma etching process to prevent electr...
- Patent number 9,939,710
- Issue date Apr 10, 2018
- Texas Instruments Incorporated
- Neng Jiang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Piezoeletric wet etch process with reduced resist lifting and contr...
- Patent number 9,755,139
- Issue date Sep 5, 2017
- Texas Instruments Incorporated
- Neng Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-temperature isotropic plasma etching process to prevent electr...
- Patent number 9,405,089
- Issue date Aug 2, 2016
- Texas Instruments Incorporated
- Neng Jiang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Bond-pad integration scheme for improved moisture barrier and elect...
- Patent number 9,304,283
- Issue date Apr 5, 2016
- Texas Instruments Incorporated
- Joel Soman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods and apparatus to reduce semiconductor wafer warpage in the...
- Patent number 9,245,855
- Issue date Jan 26, 2016
- Texas Instruments Incorporated
- Simon Y S Chang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Process and apparatus for detecting aberrations in production proce...
- Patent number 4,846,928
- Issue date Jul 11, 1989
- Texas Instruments, Incorporated
- Steven B. Dolins
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PIEZOELETRIC WET ETCH PROCESS WITH REDUCED RESIST LIFTING AND CONTR...
- Publication number 20170338401
- Publication date Nov 23, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Neng Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-TEMPERATURE ISOTROPIC PLASMA ETCHING PROCESS TO PREVENT ELECTR...
- Publication number 20160313627
- Publication date Oct 27, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Neng Jiang
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PIEZOELETRIC WET ETCH PROCESS WITH REDUCED RESIST LIFTING AND CONTR...
- Publication number 20150380637
- Publication date Dec 31, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Neng Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Apparatus to Reduce Semiconductor Wafer Warpage in the...
- Publication number 20150380363
- Publication date Dec 31, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Simon YS Chang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
BOND-PAD INTEGRATION SCHEME FOR IMPROVED MOISTURE BARRIER AND ELECT...
- Publication number 20150338604
- Publication date Nov 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Joel Soman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
HIGH-TEMPERATURE ISOTROPIC PLASMA ETCHING PROCESS TO PREVENT ELECTR...
- Publication number 20150340245
- Publication date Nov 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Neng Jiang
- H01 - BASIC ELECTRIC ELEMENTS

Thomas Warren Lassiter

Person

Patents Grantslast 30 patents

Method of forming a semiconductor device

High-temperature isotropic plasma etching process to prevent electr...

Piezoeletric wet etch process with reduced resist lifting and contr...

High-temperature isotropic plasma etching process to prevent electr...

Bond-pad integration scheme for improved moisture barrier and elect...

Methods and apparatus to reduce semiconductor wafer warpage in the...

Process and apparatus for detecting aberrations in production proce...

Patents Applicationslast 30 patents

PIEZOELETRIC WET ETCH PROCESS WITH REDUCED RESIST LIFTING AND CONTR...

HIGH-TEMPERATURE ISOTROPIC PLASMA ETCHING PROCESS TO PREVENT ELECTR...

PIEZOELETRIC WET ETCH PROCESS WITH REDUCED RESIST LIFTING AND CONTR...

Methods and Apparatus to Reduce Semiconductor Wafer Warpage in the...

BOND-PAD INTEGRATION SCHEME FOR IMPROVED MOISTURE BARRIER AND ELECT...

HIGH-TEMPERATURE ISOTROPIC PLASMA ETCHING PROCESS TO PREVENT ELECTR...