Thuong Quang Truong

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Avoiding deadlocks in processor-based systems employing retry and i...
- Patent number 9,990,291
- Issue date Jun 5, 2018
- QUALCOMM Incorporated
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining cache coherency using conditional intervention among mu...
- Patent number 9,921,962
- Issue date Mar 20, 2018
- QUALCOMM Incorporated
- Kun Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridging strongly ordered write transactions to devices in weakly o...
- Patent number 9,594,713
- Issue date Mar 14, 2017
- QUALCOMM Incorporated
- Randall John Pascarella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance monitor design for instruction profiling using shared c...
- Patent number 8,601,193
- Issue date Dec 3, 2013
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance monitor design for counting events generated by thread...
- Patent number 8,589,922
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing sampled instruction address registers for efficient instruc...
- Patent number 8,489,787
- Issue date Jul 16, 2013
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for cache coherency in a multiprocessor system
- Patent number 8,397,029
- Issue date Mar 12, 2013
- International Business Machines Corporation
- Richard Nicholas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for optimizing neighboring cache usage in a multi...
- Patent number 8,296,520
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for communicating command parameters between a processor and...
- Patent number 8,024,489
- Issue date Sep 20, 2011
- International Business Machines Corporation
- Michael N. Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing livelocks in processor selection of load requests
- Patent number 8,015,565
- Issue date Sep 6, 2011
- International Business Machines Corporation
- Richard William Doing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus controller initiated write-through mechanism with hardware auto...
- Patent number 7,877,550
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Jonathan James DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating instructions and data between a processor and externa...
- Patent number 7,869,459
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Michael N. Day
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for cache line replacement selection in a multipr...
- Patent number 7,836,257
- Issue date Nov 16, 2010
- International Business Machines Corpation
- Robert John Dorsey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined response cancellation for load command
- Patent number 7,818,509
- Issue date Oct 19, 2010
- International Business Machines Corporation
- Brian Mitchell Bass
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method to provide atomic update primitives in an asymmetric heterog...
- Patent number 7,814,281
- Issue date Oct 12, 2010
- International Business Machines Corporation
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for communicating instructions and data between a processor...
- Patent number 7,778,271
- Issue date Aug 17, 2010
- International Business Machines Corporation
- Michael N. Day
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory barriers primitives in an asymmetric heterogeneous multiproc...
- Patent number 7,725,618
- Issue date May 25, 2010
- International Business Machines Corporation
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory for multi-node coherent bus
- Patent number 7,725,660
- Issue date May 25, 2010
- International Business Machines Corporation
- Gary Dale Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing the power consumption of a data p...
- Patent number 7,721,123
- Issue date May 18, 2010
- International Business Machines Corporation
- Shigehiro Asano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and flexible trace trigger handling for non-concurrent ev...
- Patent number 7,689,870
- Issue date Mar 30, 2010
- International Business Machines Corporation
- Jason A. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory for multi-node coherent bus
- Patent number 7,669,013
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Gary Dale Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to provide cache management commands for a DMA controller
- Patent number 7,657,667
- Issue date Feb 2, 2010
- International Business Machines Corporation
- Charles Ray Johns
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reducing data storage in devices using mult...
- Patent number 7,613,841
- Issue date Nov 3, 2009
- Kabushiki Kaisha Toshiba
- Shigehiro Asano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for a processor to use locking cache as part of system me...
- Patent number 7,596,665
- Issue date Sep 29, 2009
- International Business Machines Corporation
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct deposit using locking cache
- Patent number 7,590,802
- Issue date Sep 15, 2009
- International Business Machines Corporation
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for asynchronous DMA command completion notification wherein...
- Patent number 7,546,393
- Issue date Jun 9, 2009
- International Business Machines Corporation
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for reducing store latency in symmetrical multipr...
- Patent number 7,519,780
- Issue date Apr 14, 2009
- International Business Machines Corporation
- Jonathan J. DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed address arbitration scheme for symmetrical multiprocess...
- Patent number 7,484,052
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Brian M. Bass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus controller initiated write-through mechanism
- Patent number 7,472,229
- Issue date Dec 30, 2008
- International Business Machines Corporation
- Jonathan James DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for communicating command parameters between a pr...
- Patent number 7,386,636
- Issue date Jun 10, 2008
- International Business Machines Corporation
- Michael N. Day
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SELF-AWARE, PEER-TO-PEER CACHE TRANSFERS BETWEEN LOCAL, SHARED CACH...
- Publication number 20170371783
- Publication date Dec 28, 2017
- QUALCOMM Incorporated
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING SCALABLE DYNAMIC RANDOM ACCESS MEMORY (DRAM) CACHE MANAGE...
- Publication number 20170212840
- Publication date Jul 27, 2017
- QUALCOMM Incorporated
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND I...
- Publication number 20170091098
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING CACHE COHERENCY USING CONDITIONAL INTERVENTION AMONG MU...
- Publication number 20170091095
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Kun Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRIDGING STRONGLY ORDERED WRITE TRANSACTIONS TO DEVICES IN WEAKLY O...
- Publication number 20160077991
- Publication date Mar 17, 2016
- QUALCOMM Incorporated
- Randall John Pascarella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT SNOOP INTERVENTION
- Publication number 20150074357
- Publication date Mar 12, 2015
- QUALCOMM Incorporated
- Joseph G. MCDONALD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sharing Sampled Instruction Address Registers for Efficient Instruc...
- Publication number 20120089985
- Publication date Apr 12, 2012
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performance Monitor Design for Counting Events Generated by Thread...
- Publication number 20120089979
- Publication date Apr 12, 2012
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performance Monitor Design for Instruction Profiling Using Shared C...
- Publication number 20120089984
- Publication date Apr 12, 2012
- International Business Machines Corporation
- Etai Adar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTI...
- Publication number 20090164731
- Publication date Jun 25, 2009
- Hien Minh Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Cache Coherency In A Multiprocessor System
- Publication number 20090164735
- Publication date Jun 25, 2009
- Richard Nicholas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Cache Line Replacement Selection in a Multipr...
- Publication number 20090164736
- Publication date Jun 25, 2009
- Robert John Dorsey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined Response Cancellation for Load Command
- Publication number 20090113138
- Publication date Apr 30, 2009
- Brian Mitchell Bass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bus Controller Initiated Write-Through Mechanism with Hardware Auto...
- Publication number 20090077323
- Publication date Mar 19, 2009
- International Business Machines Corporation
- Jonathan James DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Directory for Multi-Node Coherent Bus
- Publication number 20090031085
- Publication date Jan 29, 2009
- Gary Dale Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Directory For Multi-Node Coherent Bus
- Publication number 20090031086
- Publication date Jan 29, 2009
- Gary Dale Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communicating Instructions and Data Between a Processor and Externa...
- Publication number 20080288757
- Publication date Nov 20, 2008
- International Business Machines Corporation
- Michael N. Day
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System for Communicating Command Parameters Between a Processor and...
- Publication number 20080244200
- Publication date Oct 2, 2008
- International Business Machines Corporation
- Michael N. Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MANAGING THE POWER CONSUMPTION OF A DATA P...
- Publication number 20080126817
- Publication date May 29, 2008
- Shigehiro Asano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND FLEXIBLE TRACE TRIGGER HANDLING FOR NON-CONCURRENT EV...
- Publication number 20080120523
- Publication date May 22, 2008
- International Business Machines Corporation
- Jason A. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Reducing Store Latency in Symmetrical Multipr...
- Publication number 20080109585
- Publication date May 8, 2008
- Jonathan J. DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load starvation detector and buster
- Publication number 20080091883
- Publication date Apr 17, 2008
- International Business Machines Corporation
- Jason A. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maintaining forward progress in a shared L2 by detecting and breaki...
- Publication number 20080091866
- Publication date Apr 17, 2008
- International Business Machines Corporation
- Jason A. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and structure for interruting L2 cache live-lock occurrences
- Publication number 20080091879
- Publication date Apr 17, 2008
- International Business Machines Corporation
- Robert J. Dorsey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DMAC Address Translation Miss Handling Mechanism
- Publication number 20080065855
- Publication date Mar 13, 2008
- Matthew E. King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Processor to Use Locking Cache as Part of System Memory
- Publication number 20080040548
- Publication date Feb 14, 2008
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct Deposit Using Locking Cache
- Publication number 20080040549
- Publication date Feb 14, 2008
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Reducing Data Storage in Devices Using Mult...
- Publication number 20070288672
- Publication date Dec 13, 2007
- Shigehiro Asano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR ASYNCHRONOUS DMA COMMAND COMPLETION NOTIFICATION
- Publication number 20070174509
- Publication date Jul 26, 2007
- Michael Norman Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for reducing command reissue latency
- Publication number 20070174556
- Publication date Jul 26, 2007
- International Business Machines Corporation
- Jeffrey D. Brown
- G06 - COMPUTING CALCULATING COUNTING

Thuong Quang Truong

Person

Patents Grantslast 30 patents

Avoiding deadlocks in processor-based systems employing retry and i...

Maintaining cache coherency using conditional intervention among mu...

Bridging strongly ordered write transactions to devices in weakly o...

Performance monitor design for instruction profiling using shared c...

Performance monitor design for counting events generated by thread...

Sharing sampled instruction address registers for efficient instruc...

System and method for cache coherency in a multiprocessor system

System and method for optimizing neighboring cache usage in a multi...

System for communicating command parameters between a processor and...

Preventing livelocks in processor selection of load requests

Bus controller initiated write-through mechanism with hardware auto...

Communicating instructions and data between a processor and externa...

System and method for cache line replacement selection in a multipr...

Combined response cancellation for load command

Method to provide atomic update primitives in an asymmetric heterog...

Method for communicating instructions and data between a processor...

Memory barriers primitives in an asymmetric heterogeneous multiproc...

Directory for multi-node coherent bus

Method and apparatus for managing the power consumption of a data p...

Efficient and flexible trace trigger handling for non-concurrent ev...

Directory for multi-node coherent bus

Method to provide cache management commands for a DMA controller

Systems and methods for reducing data storage in devices using mult...

Mechanism for a processor to use locking cache as part of system me...

Direct deposit using locking cache

System for asynchronous DMA command completion notification wherein...

System and method for reducing store latency in symmetrical multipr...

Distributed address arbitration scheme for symmetrical multiprocess...

Bus controller initiated write-through mechanism

System and method for communicating command parameters between a pr...

Patents Applicationslast 30 patents

SELF-AWARE, PEER-TO-PEER CACHE TRANSFERS BETWEEN LOCAL, SHARED CACH...

PROVIDING SCALABLE DYNAMIC RANDOM ACCESS MEMORY (DRAM) CACHE MANAGE...

AVOIDING DEADLOCKS IN PROCESSOR-BASED SYSTEMS EMPLOYING RETRY AND I...

MAINTAINING CACHE COHERENCY USING CONDITIONAL INTERVENTION AMONG MU...

BRIDGING STRONGLY ORDERED WRITE TRANSACTIONS TO DEVICES IN WEAKLY O...

DIRECT SNOOP INTERVENTION

Sharing Sampled Instruction Address Registers for Efficient Instruc...

Performance Monitor Design for Counting Events Generated by Thread...

Performance Monitor Design for Instruction Profiling Using Shared C...

SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTI...

System and Method for Cache Coherency In A Multiprocessor System

System and Method for Cache Line Replacement Selection in a Multipr...

Combined Response Cancellation for Load Command

Bus Controller Initiated Write-Through Mechanism with Hardware Auto...

Directory for Multi-Node Coherent Bus

Directory For Multi-Node Coherent Bus

Communicating Instructions and Data Between a Processor and Externa...

System for Communicating Command Parameters Between a Processor and...

METHOD AND APPARATUS FOR MANAGING THE POWER CONSUMPTION OF A DATA P...

EFFICIENT AND FLEXIBLE TRACE TRIGGER HANDLING FOR NON-CONCURRENT EV...

System and Method for Reducing Store Latency in Symmetrical Multipr...

Load starvation detector and buster

Maintaining forward progress in a shared L2 by detecting and breaki...

Method and structure for interruting L2 cache live-lock occurrences

DMAC Address Translation Miss Handling Mechanism

Method for Processor to Use Locking Cache as Part of System Memory

Direct Deposit Using Locking Cache

Systems and Methods for Reducing Data Storage in Devices Using Mult...

SYSTEM FOR ASYNCHRONOUS DMA COMMAND COMPLETION NOTIFICATION

Methods and apparatus for reducing command reissue latency