Tian Lu

Person

Osceola, IN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Assembling and handling edge interconnect packaging system
- Patent number 11,523,511
- Issue date Dec 6, 2022
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Adiabatic flip-flop and memory cell design
- Patent number 11,488,660
- Issue date Nov 1, 2022
- Indiana Integrated Circuits, LLC
- Gregory Snider
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge interconnect self-assembly substrate
- Patent number 11,398,463
- Issue date Jul 26, 2022
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Edge interconnects for use with circuit boards and integrated circuits
- Patent number 11,224,126
- Issue date Jan 11, 2022
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Assembling and handling edge interconnect packaging system
- Patent number 10,945,335
- Issue date Mar 9, 2021
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Edge interconnect self-assembly substrate
- Patent number 10,896,898
- Issue date Jan 19, 2021
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system to passively align and attach fiber array to lase...
- Patent number 10,598,861
- Issue date Mar 24, 2020
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- G02 - OPTICS
Information Patent Grant
Method and system to passively align and attach fiber array to lase...
- Patent number 10,409,004
- Issue date Sep 10, 2019
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- G02 - OPTICS
Information Patent Grant
Substrates with interdigitated hinged edge interconnects
- Patent number 10,182,498
- Issue date Jan 15, 2019
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Prototyping of electronic circuits with edge interconnects
- Patent number 10,056,335
- Issue date Aug 21, 2018
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of interconnecting microchips
- Patent number 9,844,139
- Issue date Dec 12, 2017
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Prototyping of electronic circuits with edge interconnects
- Patent number 9,806,030
- Issue date Oct 31, 2017
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Adiabatic Flip-Flop and Memory Cell Design
- Publication number 20210327496
- Publication date Oct 21, 2021
- Indiana Integrated Circuits, LLC
- Gregory Snider
- G11 - INFORMATION STORAGE
Information Patent Application
Assembling and Handling Edge Interconnect Packaging System
- Publication number 20210168938
- Publication date Jun 3, 2021
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Edge Interconnect Self-Assembly Substrate
- Publication number 20210050335
- Publication date Feb 18, 2021
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge Interconnects for Use With Circuit Boards and Integrated Circuits
- Publication number 20210051799
- Publication date Feb 18, 2021
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and System to Passively Align and Attach Fiber Array to Lase...
- Publication number 20200003955
- Publication date Jan 2, 2020
- Indiana Integrated Circuits, LLC
- Jason M. KULICK
- G02 - OPTICS
Information Patent Application
Method and System to Passively Align and Attach Fiber Array to Lase...
- Publication number 20190250335
- Publication date Aug 15, 2019
- Indiana Integrated Circuits, LLC
- Jason M. KULICK
- G02 - OPTICS
Information Patent Application
Assembling and Handling Edge Interconnect Packaging System
- Publication number 20180077801
- Publication date Mar 15, 2018
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Prototyping of Electronic Circuits with Edge Interconnects
- Publication number 20180019208
- Publication date Jan 18, 2018
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Prototyping of Electronic Circuits with Edge Interconnects
- Publication number 20170125350
- Publication date May 4, 2017
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge Interconnect Self-Assembly Substrate
- Publication number 20170125389
- Publication date May 4, 2017
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrates with Interdigitated Hinged Edge Interconnects
- Publication number 20170127518
- Publication date May 4, 2017
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assembling and Handling Edge Interconnect Packaging System
- Publication number 20140268592
- Publication date Sep 18, 2014
- Indiana Integrated Circuits, LLC
- Jason M. Kulick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Person

Patents Grantslast 30 patents

Assembling and handling edge interconnect packaging system

Adiabatic flip-flop and memory cell design

Edge interconnect self-assembly substrate

Edge interconnects for use with circuit boards and integrated circuits

Assembling and handling edge interconnect packaging system

Edge interconnect self-assembly substrate

Method and system to passively align and attach fiber array to lase...

Method and system to passively align and attach fiber array to lase...

Substrates with interdigitated hinged edge interconnects

Prototyping of electronic circuits with edge interconnects

Method of interconnecting microchips

Prototyping of electronic circuits with edge interconnects

Patents Applicationslast 30 patents

Adiabatic Flip-Flop and Memory Cell Design

Assembling and Handling Edge Interconnect Packaging System

Edge Interconnect Self-Assembly Substrate

Edge Interconnects for Use With Circuit Boards and Integrated Circuits

Method and System to Passively Align and Attach Fiber Array to Lase...

Method and System to Passively Align and Attach Fiber Array to Lase...

Assembling and Handling Edge Interconnect Packaging System

Prototyping of Electronic Circuits with Edge Interconnects

Prototyping of Electronic Circuits with Edge Interconnects

Edge Interconnect Self-Assembly Substrate

Substrates with Interdigitated Hinged Edge Interconnects

Assembling and Handling Edge Interconnect Packaging System