Tiberiu Chelcea

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Patents Grantslast 30 patents

Information Patent Grant
Low latency FIFO circuit for mixed clock systems
- Patent number 7,197,582
- Issue date Mar 27, 2007
- Tiberiu Chelcea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency FIFO circuits for mixed asynchronous and synchronous sy...
- Patent number 6,850,092
- Issue date Feb 1, 2005
- The Trustees of Columbia University
- Tiberiu Chelcea
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low latency fifo circuits for mixed asynchronous and synchronous sy...
- Publication number 20040128413
- Publication date Jul 1, 2004
- Tiberiu Chelcea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low latency fifo circuit for mixed clock systems
- Publication number 20040125665
- Publication date Jul 1, 2004
- Tiberiu Chelcea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low latency FIFO circuits for mixed asynchronous and synchronous sy...
- Publication number 20020167337
- Publication date Nov 14, 2002
- Tiberiu Chelcea
- G06 - COMPUTING CALCULATING COUNTING