Tim Tuan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data processing array interface having interface tiles with multipl...
- Patent number 12,164,451
- Issue date Dec 10, 2024
- Xilinx, Inc.
- David Patrick Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-die integrated circuit with data processing engine array
- Patent number 12,001,367
- Issue date Jun 4, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 11,972,132
- Issue date Apr 30, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple partitions in a data processing array
- Patent number 11,848,670
- Issue date Dec 19, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-die integrated circuit with data processing engine array
- Patent number 11,693,808
- Issue date Jul 4, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-addressing mode for DMA and non-sequential read and write pat...
- Patent number 11,669,464
- Issue date Jun 6, 2023
- Xilinx, Inc.
- Goran Hk Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory tiles in data processing engine array
- Patent number 11,520,717
- Issue date Dec 6, 2022
- Xilinx, Inc.
- David Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engines with cascade connected cores
- Patent number 11,443,091
- Issue date Sep 13, 2022
- Xilinx, Inc.
- Peter McColgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable device having a data processing engine (DPE) array
- Patent number 11,386,020
- Issue date Jul 12, 2022
- Xilinx, Inc.
- Matthew H. Klein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,336,287
- Issue date May 17, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-port stream switch for stream interconnect network
- Patent number 11,323,391
- Issue date May 3, 2022
- Xilinx, Inc.
- Peter McColgan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine array architecture with memory tiles
- Patent number 11,296,707
- Issue date Apr 5, 2022
- Xilinx, Inc.
- Javier Cabezas Rodriguez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-die integrated circuit with data processing engine array
- Patent number 11,288,222
- Issue date Mar 29, 2022
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Activity-aware clock gating for switches
- Patent number 11,223,351
- Issue date Jan 11, 2022
- Xilinx, Inc.
- Amarnath Kasibhatla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing engine arrangement in a device
- Patent number 10,866,753
- Issue date Dec 15, 2020
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core for a data processing engine in an integrated circuit
- Patent number 10,747,531
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Jan Langer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip interface architecture
- Patent number 10,635,622
- Issue date Apr 28, 2020
- Xilinx, Inc.
- Goran H. K. Bilski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptively tuning an integrated circuit
- Patent number 9,444,497
- Issue date Sep 13, 2016
- Xilinx, Inc.
- Sundararajarao Mohan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time-multiplexed, asynchronous device
- Patent number 9,355,690
- Issue date May 31, 2016
- Xilinx, Inc.
- Tim Tuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimizing supply voltage and threshold voltage
- Patent number 9,348,959
- Issue date May 24, 2016
- Xilinx, Inc.
- Tim Tuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device specific configuration of operating voltage
- Patent number 9,015,023
- Issue date Apr 21, 2015
- Xilinx, Inc.
- Tim Tuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for identifying gating opportunities from a high-level lang...
- Patent number 8,443,344
- Issue date May 14, 2013
- Xilinx, Inc.
- Prasanna Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple sleep mode memory device
- Patent number 8,411,527
- Issue date Apr 2, 2013
- Xilix, Inc.
- Tim Tuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable integrated circuit with voltage domains
- Patent number 8,159,263
- Issue date Apr 17, 2012
- Xilinx, Inc.
- Tim Tuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of enabling functions of a design to be implemented in an i...
- Patent number 8,155,907
- Issue date Apr 10, 2012
- Xilinx, Inc.
- Austin H. Lesea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level circuit architecture optimizer
- Patent number 8,146,045
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Tim Tuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for the detection and compensation of integrat...
- Patent number 8,130,027
- Issue date Mar 6, 2012
- Xilinx, Inc.
- Tim Tuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling unused/inactive resources in an integrated circuit for st...
- Patent number 8,099,691
- Issue date Jan 17, 2012
- Xilinx, Inc.
- Tim Tuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power management with packaged multi-die integrated circuit
- Patent number 7,992,020
- Issue date Aug 2, 2011
- Xilinx, Inc.
- Tim Tuan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for using reconfiguration ports for power managem...
- Patent number 7,973,556
- Issue date Jul 5, 2011
- Xilinx, Inc.
- Juan J. Noguera Serra
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
- Publication number 20240088900
- Publication date Mar 14, 2024
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROCESSING ARRAY INTERFACE HAVING INTERFACE TILES WITH MULTIPL...
- Publication number 20230376437
- Publication date Nov 23, 2023
- Xilinx, Inc.
- David Patrick Clarke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY
- Publication number 20230336179
- Publication date Oct 19, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20230289311
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20230131698
- Publication date Apr 27, 2023
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH...
- Publication number 20230044581
- Publication date Feb 9, 2023
- Xilinx, Inc.
- Tim Tuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20220197846
- Publication date Jun 23, 2022
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
- Publication number 20220100691
- Publication date Mar 31, 2022
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-ON-CHIP INTERFACE ARCHITECTURE
- Publication number 20190303328
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Goran H.K. Balski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE
- Publication number 20190303033
- Publication date Oct 3, 2019
- Xilinx, Inc.
- Juan J. Noguera Serra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE
- Publication number 20110276321
- Publication date Nov 10, 2011
- Xilinx, Inc.
- Tim Tuan
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Data processing array interface having interface tiles with multipl...

Multi-die integrated circuit with data processing engine array

Data processing engine arrangement in a device

Multiple partitions in a data processing array

Multi-die integrated circuit with data processing engine array

Multi-addressing mode for DMA and non-sequential read and write pat...

Memory tiles in data processing engine array

Data processing engines with cascade connected cores

Programmable device having a data processing engine (DPE) array

Data processing engine array architecture with memory tiles

Multi-port stream switch for stream interconnect network

Data processing engine array architecture with memory tiles

Multi-die integrated circuit with data processing engine array

Activity-aware clock gating for switches

Data processing engine arrangement in a device

Core for a data processing engine in an integrated circuit

System-on-chip interface architecture

Method and apparatus for adaptively tuning an integrated circuit

Time-multiplexed, asynchronous device

Optimizing supply voltage and threshold voltage

Device specific configuration of operating voltage

Methods for identifying gating opportunities from a high-level lang...

Multiple sleep mode memory device

Programmable integrated circuit with voltage domains

Methods of enabling functions of a design to be implemented in an i...

High-level circuit architecture optimizer

Apparatus and method for the detection and compensation of integrat...

Disabling unused/inactive resources in an integrated circuit for st...

Power management with packaged multi-die integrated circuit

System and method for using reconfiguration ports for power managem...

Patents Applicationslast 30 patents

MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY

DATA PROCESSING ARRAY INTERFACE HAVING INTERFACE TILES WITH MULTIPL...

MULTIPLE PARTITIONS IN A DATA PROCESSING ARRAY

MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

LEARNING-BASED POWER MODELING OF A PROCESSOR CORE AND SYSTEMS WITH...

MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY

MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY

SYSTEM-ON-CHIP INTERFACE ARCHITECTURE

DATA PROCESSING ENGINE ARRANGEMENT IN A DEVICE

DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE