Timothy Anderson

Person

University Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Streaming engine with early and late address and loop count registe...
- Patent number 12,367,150
- Issue date Jul 22, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling the number of powered vector lanes via a register field
- Patent number 12,366,906
- Issue date Jul 22, 2025
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Padding and suppressing rows and columns of data
- Patent number 12,367,147
- Issue date Jul 22, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,360,843
- Issue date Jul 15, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Butterfly network on load data return
- Patent number 12,341,534
- Issue date Jun 24, 2025
- Texas Instruments Incorporated
- Dheera Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nested loop control
- Patent number 12,333,284
- Issue date Jun 17, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entering protected pipeline mode with clearing
- Patent number 12,321,750
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit, system, and method for matrix decimation
- Patent number 12,321,747
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-hardware memory management modes
- Patent number 12,314,187
- Issue date May 27, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector reverse
- Patent number 12,307,251
- Issue date May 20, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with stream metadata saving for context switching
- Patent number 12,299,446
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming constant extensions in the same execute packet in a VLIW pr...
- Patent number 12,265,827
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple instruction set architectures on a processing device
- Patent number 12,260,219
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Duc Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CPUs with capture queues to save and restore intermediate results a...
- Patent number 12,223,327
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of storing register data elements to interleave with data el...
- Patent number 12,217,054
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 12,204,905
- Issue date Jan 21, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pipeline control in a hierarchical memory system
- Patent number 12,197,332
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exit history based branch prediction
- Patent number 12,197,917
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing device with vector transformation execution
- Patent number 12,182,573
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE INSTRUCTION SET ARCHITECTURES ON A PROCESSING DEVICE
- Publication number 20250224957
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE...
- Publication number 20250217156
- Publication date Jul 3, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20250181238
- Publication date Jun 5, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
- Publication number 20250156185
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...
- Publication number 20250156186
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXIT HISTORY BASED BRANCH PREDICTION
- Publication number 20250147765
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION
- Publication number 20250130808
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA EL...
- Publication number 20250130797
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc Quang BUI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCT...
- Publication number 20250117247
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc BUI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NESTED LOOP CONTROL
- Publication number 20250117224
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
- Publication number 20250103502
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUICK CLEARING OF REGISTERS
- Publication number 20250044975
- Publication date Feb 6, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM
- Publication number 20250045230
- Publication date Feb 6, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David M. THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...
- Publication number 20250028645
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIASED MODE FOR CACHE CONTROLLER
- Publication number 20250021481
- Publication date Jan 16, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ADDRESS GENERATION
- Publication number 20250013467
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
- Publication number 20250013518
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING

Timothy Anderson

Person

Patents Grantslast 30 patents

Streaming engine with early and late address and loop count registe...

Controlling the number of powered vector lanes via a register field

Padding and suppressing rows and columns of data

Multicore shared cache operation engine

Butterfly network on load data return

Nested loop control

Entering protected pipeline mode with clearing

Methods and apparatus to facilitate atomic operations in victim cache

Victim cache with write miss merging

Circuit, system, and method for matrix decimation

Software-hardware memory management modes

Vector reverse

Streaming engine with stream metadata saving for context switching

Write merging on stores with different privilege levels

Hybrid victim cache and write miss buffer with fence operation

Forming constant extensions in the same execute packet in a VLIW pr...

Methods and apparatus for multi-banked victim cache with dual datapath

Multiple instruction set architectures on a processing device

CPUs with capture queues to save and restore intermediate results a...

Multicore, multibank, fully concurrent coherence controller

Method of storing register data elements to interleave with data el...

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Inserting predefined pad values into a stream of vectors

Memory pipeline control in a hierarchical memory system

Methods and apparatus to reduce bank pressure using aggressive writ...

Exit history based branch prediction

Fully pipelined read-modify-write support

Methods and apparatus for allocation in a victim cache system

Processing device with vector transformation execution

Patents Applicationslast 30 patents

MULTIPLE INSTRUCTION SET ARCHITECTURES ON A PROCESSING DEVICE

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE...

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

EXIT HISTORY BASED BRANCH PREDICTION

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION

METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA EL...

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCT...

NESTED LOOP CONTROL

MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM

MULTICORE SHARED CACHE OPERATION ENGINE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

QUICK CLEARING OF REGISTERS

BUS ARCHITECTURE WITH TRANSACTION CREDIT SYSTEM

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PADDING IN A STREAM OF MATRIX ELEMENTS

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

ALIASED MODE FOR CACHE CONTROLLER

CACHE COHERENCE SHARED STATE SUPPRESSION

STREAMING ADDRESS GENERATION

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING