Timothy E. Fiscus

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay inversely proportional to temperature timer circuit
- Patent number 7,642,833
- Issue date Jan 5, 2010
- Cypress Semiconductor Corporation
- Chris Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and architecture for reducing the power consumption for memo...
- Patent number 7,057,960
- Issue date Jun 6, 2006
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply detecting input receiver circuit and method
- Patent number 6,970,032
- Issue date Nov 29, 2005
- Cypress Semiconductor Corporation
- Chris Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Proportional to temperature voltage generator
- Patent number 6,901,022
- Issue date May 31, 2005
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for performing memory operations of a memory device
- Patent number 6,735,140
- Issue date May 11, 2004
- Cypress Semiconductor Corporation
- Tim Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and architecture for self-clocking digital delay locked loop
- Patent number 6,731,147
- Issue date May 4, 2004
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and architecture for refreshing a 1T memory proportional to...
- Patent number 6,714,473
- Issue date Mar 30, 2004
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for guaranteeing a minimum data strobe valid window and a mi...
- Patent number 6,708,298
- Issue date Mar 16, 2004
- International Business Machines Corporation
- William E. Corbin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing and guaranteeing that skew between two signals m...
- Patent number 6,658,604
- Issue date Dec 2, 2003
- International Business Machines Corporation
- William R. Corbin
- G11 - INFORMATION STORAGE
Information Patent Grant
Proportional to temperature voltage generator
- Patent number 6,628,558
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Digitally controlled analog delay locked loop (DLL)
- Patent number 6,628,154
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and architecture for reducing the power consumption for memo...
- Patent number 6,618,314
- Issue date Sep 9, 2003
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Data and data strobe circuits and operating protocol for double dat...
- Patent number 6,529,993
- Issue date Mar 4, 2003
- International Business Machines Corp.
- Jim L. Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-divider architecture for low power in a digital delay locked loop
- Patent number 6,492,852
- Issue date Dec 10, 2002
- International Business Machines Corporation
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Setting the common mode level of a differential charge pump output
- Patent number 6,255,873
- Issue date Jul 3, 2001
- Intel Corporation
- Luke A. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Setting the common mode level of a differential charge pump output
- Patent number 6,184,732
- Issue date Feb 6, 2001
- Intel Corporation
- Luke A. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable delay cell with a self-biasing load
- Patent number 5,994,939
- Issue date Nov 30, 1999
- Intel Corporation
- Luke A. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Proportional to temperature voltage generator
- Publication number 20030198114
- Publication date Oct 23, 2003
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Application
Method and architecture for self-clocking digital delay locked loop
- Publication number 20030080791
- Publication date May 1, 2003
- CYPRESS SEMICONDUCTOR CORP.
- Timothy E. Fiscus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digitally controlled analog delay locked loop (DLL)
- Publication number 20030025539
- Publication date Feb 6, 2003
- CYPRESS SEMICONDUCTOR CORP.
- Timothy E. Fiscus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Proportional to temperature voltage generator
- Publication number 20020196692
- Publication date Dec 26, 2002
- CYPRESS SEMICONDUCTOR CORP.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-DIVIDER ARCHITECTURE FOR LOW POWER IN A DIGITAL DELAY LOCKED LOOP
- Publication number 20020140471
- Publication date Oct 3, 2002
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Application
Method for guaranteeing a minimum data strobe valid window and a mi...
- Publication number 20020099987
- Publication date Jul 25, 2002
- International Business Machines Corporation
- William R. Corbin
- G11 - INFORMATION STORAGE

Timothy E. Fiscus

Person

Patents Grantslast 30 patents

Delay inversely proportional to temperature timer circuit

Method and architecture for reducing the power consumption for memo...

Power supply detecting input receiver circuit and method

Proportional to temperature voltage generator

Method and system for performing memory operations of a memory device

Method and architecture for self-clocking digital delay locked loop

Method and architecture for refreshing a 1T memory proportional to...

Method for guaranteeing a minimum data strobe valid window and a mi...

Method for testing and guaranteeing that skew between two signals m...

Proportional to temperature voltage generator

Digitally controlled analog delay locked loop (DLL)

Method and architecture for reducing the power consumption for memo...

Data and data strobe circuits and operating protocol for double dat...

Pre-divider architecture for low power in a digital delay locked loop

Setting the common mode level of a differential charge pump output

Setting the common mode level of a differential charge pump output

Variable delay cell with a self-biasing load

Patents Applicationslast 30 patents

Proportional to temperature voltage generator

Method and architecture for self-clocking digital delay locked loop

Digitally controlled analog delay locked loop (DLL)

Proportional to temperature voltage generator

PRE-DIVIDER ARCHITECTURE FOR LOW POWER IN A DIGITAL DELAY LOCKED LOOP

Method for guaranteeing a minimum data strobe valid window and a mi...