Timothy M. Skergan

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Calibration of an on-die thermal sensor
- Patent number 8,734,006
- Issue date May 27, 2014
- International Business Machines Corporation
- James M. Crafts
- G01 - MEASURING TESTING
Information Patent Grant
Preventing circumvention of function disablement in an information...
- Patent number 8,365,006
- Issue date Jan 29, 2013
- International Business Machines Corporation
- Steven M. Douskey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating scan chain definition from high-level model using high-lev...
- Patent number 8,281,279
- Issue date Oct 2, 2012
- International Business Machines Corporation
- William B. Maloney
- G01 - MEASURING TESTING
Information Patent Grant
Providing low-level hardware access to in-band and out-of-band firm...
- Patent number 8,090,823
- Issue date Jan 3, 2012
- International Business Machines Corporation
- James Stephen Fields, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for LBIST testing of an electronic circuit
- Patent number 8,086,925
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Benjamin Robert Gass
- G01 - MEASURING TESTING
Information Patent Grant
Method for indirect access to a support interface for memory-mapped...
- Patent number 7,916,722
- Issue date Mar 29, 2011
- International Business Machines Corporation
- James Stephen Fields, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for testing an electronic circuit to identify mul...
- Patent number 7,895,490
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Benjamin Robert Gass
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for logic built-in self-test diagnostics of integrated c...
- Patent number 7,856,582
- Issue date Dec 21, 2010
- International Business Machines Corporation
- Daniel W. Cervantes
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for manipulating a plurality of graphical pointers
- Patent number 7,696,979
- Issue date Apr 13, 2010
- International Business Machines Coporation
- Timothy Michael Skergan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to reduce LBIST manufacturing test time of integr...
- Patent number 7,519,889
- Issue date Apr 14, 2009
- International Business Machines Corporation
- Daniel W. Cervantes
- G01 - MEASURING TESTING
Information Patent Grant
Method for providing low-level hardware access to in-band and out-o...
- Patent number 7,467,204
- Issue date Dec 16, 2008
- International Business Machines Corporation
- James Stephen Fields, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for indirect access to a support interface for memory-mapped...
- Patent number 7,418,541
- Issue date Aug 26, 2008
- International Business Machines Corporation
- James Stephen Fields, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built in self test circuit for measuring total timing uncertainty i...
- Patent number 7,400,555
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Robert L. Franch
- G01 - MEASURING TESTING
Information Patent Grant
Measuring microprocessor susceptibility to internal noise generation
- Patent number 7,313,747
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Grant
Test method for guaranteeing full stuck-at-fault coverage of a memo...
- Patent number 7,073,106
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Jose A. Paredes
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing path delays in a high-speed bounda...
- Patent number 6,748,563
- Issue date Jun 8, 2004
- International Business Machines Corporation
- Johnny James LeBlanc
- G01 - MEASURING TESTING
Information Patent Grant
Globally distributed scan blocks
- Patent number 6,665,828
- Issue date Dec 16, 2003
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for scanning free-running logic
- Patent number 6,654,917
- Issue date Nov 25, 2003
- International Business Machines Corporation
- Michael Stephen Floyd
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for dynamically configuring a central processing...
- Patent number 6,550,020
- Issue date Apr 15, 2003
- International Business Machines Corporation
- Michael Stephen Floyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing IEEE 1149.1 compliant boundar...
- Patent number 6,539,491
- Issue date Mar 25, 2003
- International Business Machines Corporation
- Timothy M. Skergan
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for scanning and clocking chips with a high-sp...
- Patent number 6,452,435
- Issue date Sep 17, 2002
- International Business Machines Corporation
- Timothy M. Skergan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for phase alignment of a plurality of clock pulse...
- Patent number 6,333,653
- Issue date Dec 25, 2001
- International Business Machines Corporation
- Michael Stephen Floyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed clock having a programmable run length
- Patent number 6,226,345
- Issue date May 1, 2001
- International Business Machines Corporation
- Timothy Michael Skergan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual cache directories with respective queue independently executin...
- Patent number 6,085,288
- Issue date Jul 4, 2000
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual associative-cache directories allowing simultaneous read opera...
- Patent number 6,023,746
- Issue date Feb 8, 2000
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic updating of repair mask used for cache defect avoidance
- Patent number 6,006,311
- Issue date Dec 21, 1999
- Internatinal Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache array defect functional bypassing using repair mask
- Patent number 5,958,068
- Issue date Sep 28, 1999
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple cache directories for non-arbitration concurrent accessing...
- Patent number 5,943,686
- Issue date Aug 24, 1999
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for recoverability via redundant cache arrays
- Patent number 5,883,904
- Issue date Mar 16, 1999
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control scheme for on-chip capacitor degating
- Patent number 5,874,854
- Issue date Feb 23, 1999
- International Business Machines Corporation
- Timothy Michael Skergan
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
CALIBRATION OF AN ON-DIE THERMAL SENSOR
- Publication number 20120224602
- Publication date Sep 6, 2012
- International Business Machines Corporation
- James M. CRAFTS
- G01 - MEASURING TESTING
Information Patent Application
Creating Scan Chain Definition from High-Level Model Using High-Lev...
- Publication number 20120151288
- Publication date Jun 14, 2012
- International Business Machines Corporation
- William B. Maloney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREVENTING CIRCUMVENTION OF FUNCTION DISABLEMENT IN AN INFORMATION...
- Publication number 20120017109
- Publication date Jan 19, 2012
- International Business Machines Corporation
- Steven M. Douskey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRAT...
- Publication number 20090327824
- Publication date Dec 31, 2009
- International Business Machines Corporation
- ABEL ALANIZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Testing an Electronic Circuit
- Publication number 20090292963
- Publication date Nov 26, 2009
- International Business Machines Corporation
- Benjamin Robert Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Testing an Electronic Circuit to Identify Mul...
- Publication number 20090292964
- Publication date Nov 26, 2009
- International Business Machines Corporation
- Benjamin Robert Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Logic Built-In Self-Test Diagnostics of Integrated C...
- Publication number 20090254788
- Publication date Oct 8, 2009
- Daniel W. Cervantes
- G01 - MEASURING TESTING
Information Patent Application
Method for Providing Low-Level Hardware Access to In-Band and Out-o...
- Publication number 20090055563
- Publication date Feb 26, 2009
- International Business Machines Corporation
- James Stephen Fields, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Indirect Access to a Support Interface for Memory-Mapped...
- Publication number 20080247415
- Publication date Oct 9, 2008
- International Business Machine Corporation
- James Stephen Fields
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Integrated Circuit Control for in Situ Impedan...
- Publication number 20080224714
- Publication date Sep 18, 2008
- Tanit Virutchapunt
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINT...
- Publication number 20080198699
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Robert L. Franch
- G01 - MEASURING TESTING
Information Patent Application
DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCE...
- Publication number 20080198700
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Robert L. Franch
- G01 - MEASURING TESTING
Information Patent Application
Measuring microprocessor susceptibility to internal noise generation
- Publication number 20070236299
- Publication date Oct 11, 2007
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Application
Method for indirect access to a support interface for memory-mapped...
- Publication number 20060176897
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James Stephen Fields
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for providing low-level hardware access to in-band and out-o...
- Publication number 20060179184
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James Stephen Fields
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Built in self test circuit for measuring total timing uncertainty i...
- Publication number 20050107970
- Publication date May 19, 2005
- Robert L. Franch
- G01 - MEASURING TESTING
Information Patent Application
Test method for guaranteeing full stuck-at-fault coverage of a memo...
- Publication number 20040199816
- Publication date Oct 7, 2004
- International Business Machines Corporation
- Jose A. Paredes
- G11 - INFORMATION STORAGE

Timothy M. Skergan

Person

Patents Grantslast 30 patents

Calibration of an on-die thermal sensor

Preventing circumvention of function disablement in an information...

Creating scan chain definition from high-level model using high-lev...

Providing low-level hardware access to in-band and out-of-band firm...

Method and system for LBIST testing of an electronic circuit

Method for indirect access to a support interface for memory-mapped...

Method and system for testing an electronic circuit to identify mul...

Techniques for logic built-in self-test diagnostics of integrated c...

Method and system for manipulating a plurality of graphical pointers

System and method to reduce LBIST manufacturing test time of integr...

Method for providing low-level hardware access to in-band and out-o...

Method for indirect access to a support interface for memory-mapped...

Built in self test circuit for measuring total timing uncertainty i...

Measuring microprocessor susceptibility to internal noise generation

Test method for guaranteeing full stuck-at-fault coverage of a memo...

Method and apparatus for testing path delays in a high-speed bounda...

Globally distributed scan blocks

Method and apparatus for scanning free-running logic

Method and system for dynamically configuring a central processing...

Method and apparatus for implementing IEEE 1149.1 compliant boundar...

Method and apparatus for scanning and clocking chips with a high-sp...

System and method for phase alignment of a plurality of clock pulse...

High speed clock having a programmable run length

Dual cache directories with respective queue independently executin...

Dual associative-cache directories allowing simultaneous read opera...

Dynamic updating of repair mask used for cache defect avoidance

Cache array defect functional bypassing using repair mask

Multiple cache directories for non-arbitration concurrent accessing...

Method for recoverability via redundant cache arrays

Control scheme for on-chip capacitor degating

Patents Applicationslast 30 patents

CALIBRATION OF AN ON-DIE THERMAL SENSOR

Creating Scan Chain Definition from High-Level Model Using High-Lev...

PREVENTING CIRCUMVENTION OF FUNCTION DISABLEMENT IN AN INFORMATION...

TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRAT...

Method and System for Testing an Electronic Circuit

Method and System for Testing an Electronic Circuit to Identify Mul...

Techniques for Logic Built-In Self-Test Diagnostics of Integrated C...

Method for Providing Low-Level Hardware Access to In-Band and Out-o...

Method for Indirect Access to a Support Interface for Memory-Mapped...

System and Method of Integrated Circuit Control for in Situ Impedan...

METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINT...

DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCE...

Measuring microprocessor susceptibility to internal noise generation

Method for indirect access to a support interface for memory-mapped...

Method for providing low-level hardware access to in-band and out-o...

Built in self test circuit for measuring total timing uncertainty i...

Test method for guaranteeing full stuck-at-fault coverage of a memo...