Timothy Vanderhoek

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient logic blocks architectures for dense mapping of multipliers
- Patent number 11,768,661
- Issue date Sep 26, 2023
- Intel Corporation
- Sadegh Yazdanshenas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance FPGA addition
- Patent number 10,340,920
- Issue date Jul 2, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined direct drive routing fabric
- Patent number 9,100,011
- Issue date Aug 4, 2015
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for power management in integrated circuits
- Patent number 8,732,635
- Issue date May 20, 2014
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing delay annotation
- Patent number 8,661,385
- Issue date Feb 25, 2014
- Altera Corporation
- Lyndon Francis Carvalho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asymmetric signal routing in a programmable logic device
- Patent number 8,643,399
- Issue date Feb 4, 2014
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for optimizing the performance of programmabl...
- Patent number 8,103,975
- Issue date Jan 24, 2012
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architectures and methods for implementin...
- Patent number 7,716,623
- Issue date May 11, 2010
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Caching technique for electrical simulation of VLSI interconnect
- Patent number 7,693,700
- Issue date Apr 6, 2010
- Altera Corporation
- Tim Vanderhoek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device architectures and methods for implementin...
- Patent number 7,619,443
- Issue date Nov 17, 2009
- Altera Corporation
- Tim Vanderhoek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for power management in integrated circuits
- Patent number 7,405,589
- Issue date Jul 29, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for optimizing the performance of programmabl...
- Patent number 7,400,167
- Issue date Jul 15, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Organizations of logic modules in programmable logic devices
- Patent number 7,368,944
- Issue date May 6, 2008
- Altera Corporation
- Michael D Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for designing systems using logic regions
- Patent number 7,197,734
- Issue date Mar 27, 2007
- Altera Corporation
- Deshanand P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Organizations of logic modules in programmable logic devices
- Patent number 7,176,718
- Issue date Feb 13, 2007
- Altera Corporation
- Michael D Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT LOGIC BLOCKS ARCHITECTURES FOR DENSE MAPPING OF MULTIPLIERS
- Publication number 20240028295
- Publication date Jan 25, 2024
- Intel Corporation
- Sadegh Yazdanshenas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
- Publication number 20210200514
- Publication date Jul 1, 2021
- Intel Corporation
- Sadegh Yazdanshenas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20140258956
- Publication date Sep 11, 2014
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Methods for Optimizing the Performance of Programmabl...
- Publication number 20120089958
- Publication date Apr 12, 2012
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABL...
- Publication number 20080263490
- Publication date Oct 23, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20080263481
- Publication date Oct 23, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for optimizing the performance of programmabl...
- Publication number 20070040577
- Publication date Feb 22, 2007
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for power management in integrated circuits
- Publication number 20070040576
- Publication date Feb 22, 2007
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING

Timothy Vanderhoek

Person

Patents Grantslast 30 patents

Efficient logic blocks architectures for dense mapping of multipliers

High performance FPGA addition

Pipelined direct drive routing fabric

Apparatus and methods for power management in integrated circuits

Method and apparatus for performing delay annotation

Asymmetric signal routing in a programmable logic device

Apparatus and methods for optimizing the performance of programmabl...

Programmable logic device architectures and methods for implementin...

Caching technique for electrical simulation of VLSI interconnect

Programmable logic device architectures and methods for implementin...

Apparatus and methods for power management in integrated circuits

Apparatus and methods for optimizing the performance of programmabl...

Organizations of logic modules in programmable logic devices

Method and apparatus for designing systems using logic regions

Organizations of logic modules in programmable logic devices

Patents Applicationslast 30 patents

EFFICIENT LOGIC BLOCKS ARCHITECTURES FOR DENSE MAPPING OF MULTIPLIERS

Efficient Logic Blocks Architectures for Dense Mapping of Multipliers

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

Apparatus and Methods for Optimizing the Performance of Programmabl...

APPARATUS AND METHODS FOR OPTIMIZING THE PERFORMANCE OF PROGRAMMABL...

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

Apparatus and methods for optimizing the performance of programmabl...

Apparatus and methods for power management in integrated circuits