Ting-Sheng Ku

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fast triggering electrostatic discharge protection
- Patent number 11,804,708
- Issue date Oct 31, 2023
- NVIDIA Corp.
- Jauwen Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-die techniques for asynchnorously comparing voltages
- Patent number 11,777,483
- Issue date Oct 3, 2023
- NVIDIA Corporation
- Nishit Harshad Shah
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout parasitics and device parameter prediction using graph neura...
- Patent number 11,651,194
- Issue date May 16, 2023
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die techniques for converting currents to frequencies
- Patent number 11,619,661
- Issue date Apr 4, 2023
- NVIDIA Corporation
- Nishit Harshad Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for integrated circuit calibration
- Patent number 8,793,091
- Issue date Jul 29, 2014
- NVIDIA Corporation
- Ting Ku
- G01 - MEASURING TESTING
Information Patent Grant
Loopback configuration for bi-directional interfaces
- Patent number 8,724,483
- Issue date May 13, 2014
- NVIDIA Corporation
- Ting Sheng Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for a free running strobe tolerant interface
- Patent number 8,453,019
- Issue date May 28, 2013
- NVIDIA Corporation
- Russell Newcomb
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for sampling a data signal in a manner indepen...
- Patent number 8,194,812
- Issue date Jun 5, 2012
- NVIDIA Corporation
- Ting-Sheng Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Calibration of separate delay effects for multiple data strobe signals
- Patent number 7,755,402
- Issue date Jul 13, 2010
- NVidia
- Ting-Sheng Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit technique to prevent device overstress
- Patent number 7,619,444
- Issue date Nov 17, 2009
- NVIDIA Corporation
- Ashfaq R. Shaikh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input/output buffer for wide supply voltage range
- Patent number 7,570,088
- Issue date Aug 4, 2009
- NVIDIA Corporation
- Ting-Sheng Ku
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data sampling clock edge placement training for high speed GPU-memo...
- Patent number 7,567,104
- Issue date Jul 28, 2009
- NVIDIA Corporation
- Ting-Sheng Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit technique to achieve power up tristate on a memory bus
- Patent number 7,541,835
- Issue date Jun 2, 2009
- NVIDIA Corporation
- Ashfaq R. Shaikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus termination scheme having concurrently powered-on transistors
- Patent number 7,411,415
- Issue date Aug 12, 2008
- Ashfaq Shaikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pre-emphasis driver control
- Patent number 7,323,907
- Issue date Jan 29, 2008
- Ting-Sheng Ku
- G11 - INFORMATION STORAGE
Information Patent Grant
Data sampling clock edge placement training for high speed GPU-memo...
- Patent number 7,259,606
- Issue date Aug 21, 2007
- NVIDIA Corporation
- Ting-Sheng Ku
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ON-DIE TECHNIQUES FOR ASYNCHNOROUSLY COMPARING VOLTAGES
- Publication number 20230299760
- Publication date Sep 21, 2023
- NVIDIA Corporation
- Nishit Harshad SHAH
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Layout Parasitics and Device Parameter Prediction using Graph Neura...
- Publication number 20230237313
- Publication date Jul 27, 2023
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST TRIGGERING ELECTROSTATIC DISCHARGE PROTECTION
- Publication number 20210281067
- Publication date Sep 9, 2021
- NVIDIA Corp.
- Jauwen Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURA...
- Publication number 20210158127
- Publication date May 27, 2021
- NVIDIA Corp.
- Haoxing Ren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CALIBRATION
- Publication number 20090259425
- Publication date Oct 15, 2009
- NVIDIA Corporation
- Ting Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for a free running strobe tolerant interface
- Publication number 20090119532
- Publication date May 7, 2009
- Russell Newcomb
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Loopback configuration for bi-directional interfaces
- Publication number 20090103443
- Publication date Apr 23, 2009
- Ting Sheng Ku
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data Sampling Clock Edge Placement Training for High Speed GPU-Memo...
- Publication number 20080191771
- Publication date Aug 14, 2008
- NVIDIA Corporation
- Ting-Sheng Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data sampling clock edge placement training for high speed GPU-memo...
- Publication number 20050265064
- Publication date Dec 1, 2005
- NVIDIA Corporation
- Ting-Sheng Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bus termination scheme
- Publication number 20050218927
- Publication date Oct 6, 2005
- Ashfaq Shaikh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ting-Sheng Ku

Person

Patents Grantslast 30 patents

Fast triggering electrostatic discharge protection

On-die techniques for asynchnorously comparing voltages

Layout parasitics and device parameter prediction using graph neura...

On-die techniques for converting currents to frequencies

System and method for integrated circuit calibration

Loopback configuration for bi-directional interfaces

Method and system for a free running strobe tolerant interface

Apparatus and method for sampling a data signal in a manner indepen...

Calibration of separate delay effects for multiple data strobe signals

Circuit technique to prevent device overstress

Input/output buffer for wide supply voltage range

Data sampling clock edge placement training for high speed GPU-memo...

Circuit technique to achieve power up tristate on a memory bus

Bus termination scheme having concurrently powered-on transistors

Pre-emphasis driver control

Data sampling clock edge placement training for high speed GPU-memo...

Patents Applicationslast 30 patents

ON-DIE TECHNIQUES FOR ASYNCHNOROUSLY COMPARING VOLTAGES

Layout Parasitics and Device Parameter Prediction using Graph Neura...

FAST TRIGGERING ELECTROSTATIC DISCHARGE PROTECTION

LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURA...

SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CALIBRATION

Method and system for a free running strobe tolerant interface

Loopback configuration for bi-directional interfaces

Data Sampling Clock Edge Placement Training for High Speed GPU-Memo...

Data sampling clock edge placement training for high speed GPU-memo...

Bus termination scheme