Tobias Werner

Person

Weil im Schoenbuch, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit including logic circuitry
- Patent number 11,328,110
- Issue date May 10, 2022
- International Business Machines Corporation
- Juergen Pille
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with vertical structures on nodes of a grid
- Patent number 11,171,142
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device with a memory element utilizing stacked vert...
- Patent number 11,164,879
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried conductive layer supplying digital circuits
- Patent number 10,833,089
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device utilizing stacked vertical devices
- Patent number 10,804,266
- Issue date Oct 13, 2020
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistor placement optimization for improved leaf ce...
- Patent number 10,565,340
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field-effect transistor placement optimization for improved leaf ce...
- Patent number 10,394,994
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,997,218
- Issue date Jun 12, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout of interconnect lines in integrated circuits
- Patent number 9,904,754
- Issue date Feb 27, 2018
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of interconnect lines in integrated circuits
- Patent number 9,898,571
- Issue date Feb 20, 2018
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated stressing and testing of semiconductor memory cells
- Patent number 9,837,142
- Issue date Dec 5, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Automated stressing and testing of semiconductor memory cells
- Patent number 9,805,823
- Issue date Oct 31, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,792,967
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,786,339
- Issue date Oct 10, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,761,289
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit
- Patent number 9,711,244
- Issue date Jul 18, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM at speed flexible timing and setup control
- Patent number 9,627,090
- Issue date Apr 18, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM at speed flexible timing and setup control
- Patent number 9,627,017
- Issue date Apr 18, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Transforming a phase-locked-loop generated chip clock signal to a l...
- Patent number 9,537,474
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Yuen Hung Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,437,285
- Issue date Sep 6, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,406,375
- Issue date Aug 2, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Transforming a phase-locked-loop generated chip clock signal to a l...
- Patent number 9,401,698
- Issue date Jul 26, 2016
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM array comprising multiple cell cores
- Patent number 9,384,823
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Michael Kugel
- G11 - INFORMATION STORAGE
Information Patent Grant
Defective memory column replacement with load isolation
- Patent number 8,964,493
- Issue date Feb 24, 2015
- International Business Machines Corporation
- Silke Penth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit schematics having imbedded scaling information f...
- Patent number 8,918,749
- Issue date Dec 23, 2014
- International Business Machines Corporation
- Michael Kugel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local evaluation circuit for static random-access memory
- Patent number 8,837,235
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for generating a placement layout of a VLSI circu...
- Patent number 8,631,376
- Issue date Jan 14, 2014
- International Business Machines Corporation
- Tobias Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global bit line restore by most significant bit of an address line
- Patent number 8,587,990
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced programmable pulsewidth modulating circuit for array clock...
- Patent number 7,936,638
- Issue date May 3, 2011
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Topology for a n-way XOR/XNOR circuit
- Patent number 7,557,614
- Issue date Jul 7, 2009
- International Business Machines Corporation
- Stefan Bonsels
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MICROELECTRONIC DEVICE WITH STACKED TRANSISTORS
- Publication number 20240121934
- Publication date Apr 11, 2024
- International Business Machines Corporation
- Jens Künzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INCLUDING LOGIC CIRCUITRY
- Publication number 20210312116
- Publication date Oct 7, 2021
- International Business Machines Corporation
- Juergen Pille
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTRONIC DEVICE WITH A MEMORY ELEMENT UTILIZING STACKED VERT...
- Publication number 20200161311
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED CONDUCTIVE LAYER SUPPLYING DIGITAL CIRCUITS
- Publication number 20200161312
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE UTILIZING STACKED VERTICAL DEVICES
- Publication number 20200161300
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICAL STRUCTURES ON NODES OF A GRID
- Publication number 20200161310
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...
- Publication number 20180322235
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...
- Publication number 20180322236
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20180005674
- Publication date Jan 4, 2018
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20170243619
- Publication date Aug 24, 2017
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170228489
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170228487
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL
- Publication number 20170092341
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Application
RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL
- Publication number 20170092377
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSFORMING A PHASE-LOCKED-LOOP GENERATED CHIP CLOCK SIGNAL TO A L...
- Publication number 20160344377
- Publication date Nov 24, 2016
- International Business Machines Corporation
- Yuen Hung CHAN
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM ARRAY COMPRISING MULTIPLE CELL CORES
- Publication number 20160086659
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Michael Kugel
- G11 - INFORMATION STORAGE
Information Patent Application
Local Evaluation Circuit for Static Random-Access Memory
- Publication number 20140254290
- Publication date Sep 11, 2014
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Application
DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION
- Publication number 20140192602
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Silke Penth
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT SCHEMATICS HAVING IMBEDDED SCALING INFORMATION F...
- Publication number 20140130004
- Publication date May 8, 2014
- International Business Machines Corporation
- Michael Kugel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Generating a Placement Layout of a VLSI Circu...
- Publication number 20120174051
- Publication date Jul 5, 2012
- International Business Machines Corporation
- Tobias T. Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE
- Publication number 20120008379
- Publication date Jan 12, 2012
- International Business Machines Corporation
- Yuen H. CHAN
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for Placing Integrated Circuit Functional Blocks...
- Publication number 20120005643
- Publication date Jan 5, 2012
- International Business Machines Corporation
- Friedrich Schroeder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Circuit Arrangement for Performing a Write Through Opera...
- Publication number 20110317478
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Interleave Memory Array Arrangement
- Publication number 20110310680
- Publication date Dec 22, 2011
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK...
- Publication number 20100302895
- Publication date Dec 2, 2010
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Layout Generator for Routing and Designing an LSI
- Publication number 20080301616
- Publication date Dec 4, 2008
- International Business Machines Corporation
- Ulrich Krauch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry
- Publication number 20080258769
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Dirk Franger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for comparing two designs of electronic circuits
- Publication number 20080172640
- Publication date Jul 17, 2008
- International Business Machines Corporation
- Joachim Fenkes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic method for routing and designing an LSI
- Publication number 20050132319
- Publication date Jun 16, 2005
- International Business Machines Corporation
- Ulrich Krauch
- G06 - COMPUTING CALCULATING COUNTING

Tobias Werner

Person

Patents Grantslast 30 patents

Integrated circuit including logic circuitry

Integrated circuit with vertical structures on nodes of a grid

Microelectronic device with a memory element utilizing stacked vert...

Buried conductive layer supplying digital circuits

Microelectronic device utilizing stacked vertical devices

Field-effect transistor placement optimization for improved leaf ce...

Field-effect transistor placement optimization for improved leaf ce...

Dual mode operation having power saving and active modes in a stack...

Layout of interconnect lines in integrated circuits

Layout of interconnect lines in integrated circuits

Automated stressing and testing of semiconductor memory cells

Automated stressing and testing of semiconductor memory cells

Managing semiconductor memory array leakage current

Dual mode operation having power saving and active modes in a stack...

Managing semiconductor memory array leakage current

Memory circuit

RAM at speed flexible timing and setup control

RAM at speed flexible timing and setup control

Transforming a phase-locked-loop generated chip clock signal to a l...

Write address synchronization in 2 read/1write SRAM arrays

Write address synchronization in 2 read/1write SRAM arrays

Transforming a phase-locked-loop generated chip clock signal to a l...

SRAM array comprising multiple cell cores

Defective memory column replacement with load isolation

Integrated circuit schematics having imbedded scaling information f...

Local evaluation circuit for static random-access memory

Method and system for generating a placement layout of a VLSI circu...

Global bit line restore by most significant bit of an address line

Enhanced programmable pulsewidth modulating circuit for array clock...

Topology for a n-way XOR/XNOR circuit

Patents Applicationslast 30 patents

MICROELECTRONIC DEVICE WITH STACKED TRANSISTORS

INTEGRATED CIRCUIT INCLUDING LOGIC CIRCUITRY

MICROELECTRONIC DEVICE WITH A MEMORY ELEMENT UTILIZING STACKED VERT...

BURIED CONDUCTIVE LAYER SUPPLYING DIGITAL CIRCUITS

MICROELECTRONIC DEVICE UTILIZING STACKED VERTICAL DEVICES

INTEGRATED CIRCUIT WITH VERTICAL STRUCTURES ON NODES OF A GRID

FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...

FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL

RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL

TRANSFORMING A PHASE-LOCKED-LOOP GENERATED CHIP CLOCK SIGNAL TO A L...

SRAM ARRAY COMPRISING MULTIPLE CELL CORES

Local Evaluation Circuit for Static Random-Access Memory

DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION

INTEGRATED CIRCUIT SCHEMATICS HAVING IMBEDDED SCALING INFORMATION F...

Method and System for Generating a Placement Layout of a VLSI Circu...

GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE

System and Method for Placing Integrated Circuit Functional Blocks...

Method and Circuit Arrangement for Performing a Write Through Opera...

Interleave Memory Array Arrangement

ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK...

Layout Generator for Routing and Designing an LSI

Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry

Method for comparing two designs of electronic circuits

Automatic method for routing and designing an LSI