Todd J. DeSchepper

Person

Houston, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit for setting computer system bus signals to predetermined st...
- Patent number 6,357,013
- Issue date Mar 12, 2002
- Compaq Computer Corporation
- Philip C. Kelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with support for a subtractive agent on the seconda...
- Patent number 6,230,227
- Issue date May 8, 2001
- Compaq Computer Corp.
- Walter G. Fry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with bridge logic that includes an internal modular...
- Patent number 6,226,700
- Issue date May 1, 2001
- Compaq Computer Corporation
- Shaun Wandler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system having integrated bus bridge design with delayed tr...
- Patent number 6,212,590
- Issue date Apr 3, 2001
- Compaq Computer Corporation
- Maria L. Melo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system employing optimized delayed transaction arbitration...
- Patent number 6,199,131
- Issue date Mar 6, 2001
- Compaq Computer Corporation
- Maria L. Melo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with bridge logic that asserts a system management...
- Patent number 6,199,134
- Issue date Mar 6, 2001
- Compaq Computer Corporation
- Todd Deschepper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with enhanced docking support
- Patent number 6,145,029
- Issue date Nov 7, 2000
- Compaq Computer Corporation
- Todd Deschepper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with bridge logic that includes an internal modular...
- Patent number 6,101,566
- Issue date Aug 8, 2000
- Compaq Computer Corporation
- Robert Woods
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial bus system for sending multiple frames of unique data
- Patent number 6,094,700
- Issue date Jul 25, 2000
- Compaq Computer Corporation
- Todd Deschepper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with improved transition to low power operation
- Patent number 6,070,215
- Issue date May 30, 2000
- Compaq Computer Corporation
- Todd J. Deschepper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart battery power management in a computer system
- Patent number 6,065,122
- Issue date May 16, 2000
- Compaq Computer Corporation
- Russ Wunderlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with bridge logic that reduces interference to CPU...
- Patent number 5,991,833
- Issue date Nov 23, 1999
- Compaq Computer Corporation
- Shaun V. Wandler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic delayed transaction discard counter in a bus bridge of a co...
- Patent number 5,987,555
- Issue date Nov 16, 1999
- Compaq Computer Corporation
- Khaldoun Alzien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for switching between synchronous and asynchronous memory r...
- Patent number 5,796,992
- Issue date Aug 18, 1998
- Compaq Computer Corporation
- James R. Reif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for setting computer system bus signals to predetermined st...
- Patent number 5,740,454
- Issue date Apr 14, 1998
- Compaq Computer Corporation
- Philip C. Kelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for entering low power mode in a computer system
- Patent number 5,721,935
- Issue date Feb 24, 1998
- Compaq Computer Corporation
- Todd J. DeSchepper
- G06 - COMPUTING CALCULATING COUNTING

Todd J. DeSchepper

Person

Patents Grantslast 30 patents

Circuit for setting computer system bus signals to predetermined st...

Computer system with support for a subtractive agent on the seconda...

Computer system with bridge logic that includes an internal modular...

Computer system having integrated bus bridge design with delayed tr...

Computer system employing optimized delayed transaction arbitration...

Computer system with bridge logic that asserts a system management...

Computer system with enhanced docking support

Computer system with bridge logic that includes an internal modular...

Serial bus system for sending multiple frames of unique data

Computer system with improved transition to low power operation

Smart battery power management in a computer system

Computer system with bridge logic that reduces interference to CPU...

Dynamic delayed transaction discard counter in a bus bridge of a co...

Circuit for switching between synchronous and asynchronous memory r...

Circuit for setting computer system bus signals to predetermined st...

Apparatus and method for entering low power mode in a computer system