Todd Michael Austin

Person

Ann Arbor, MI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Privacy-enhanced computation via sequestered encryption
- Patent number 12,105,855
- Issue date Oct 1, 2024
- Agita Labs, Inc.
- Todd M Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with moving target defenses against vulnerability a...
- Patent number 11,748,490
- Issue date Sep 5, 2023
- Regents of the University of Michigan
- Todd Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Privacy-enhanced computation via sequestered encryption
- Patent number 11,748,521
- Issue date Sep 5, 2023
- Agita Labs, Inc.
- Todd M Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with moving target defenses against vulnerability a...
- Patent number 11,232,212
- Issue date Jan 25, 2022
- The Regents of the University of Michigan
- Todd Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within integrated circuit
- Patent number 10,579,463
- Issue date Mar 3, 2020
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within integrated circuit
- Patent number 10,572,334
- Issue date Feb 25, 2020
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field repairable logic
- Patent number 9,645,882
- Issue date May 9, 2017
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within integrated circuit
- Patent number 9,448,875
- Issue date Sep 20, 2016
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within integrated circuit
- Patent number 9,164,842
- Issue date Oct 20, 2015
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within integrated circuit
- Patent number 8,650,470
- Issue date Feb 11, 2014
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recover within processing stages of an integrated circuit
- Patent number 8,407,537
- Issue date Mar 26, 2013
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor and method for detecting faults therein
- Patent number 8,341,473
- Issue date Dec 25, 2012
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within processing stages of an integrated circuit
- Patent number 8,185,786
- Issue date May 22, 2012
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery within processing stages of an integrated circuit
- Patent number 8,060,814
- Issue date Nov 15, 2011
- ARM Limited
- David Theodore Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor and method for detecting faults therein
- Patent number 8,051,368
- Issue date Nov 1, 2011
- The Regents of the Univeristy of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor and method for detecting faults therein
- Patent number 7,966,538
- Issue date Jun 21, 2011
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with error correction mechanisms to offset narro...
- Patent number 7,701,240
- Issue date Apr 20, 2010
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and recovery within processing stages of an integra...
- Patent number 7,650,551
- Issue date Jan 19, 2010
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customized silicon chips produced using dynamically configurable po...
- Patent number 7,598,766
- Issue date Oct 6, 2009
- University of Washington
- Martha Mercaldi-Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method of analyzing interpreted programs
- Patent number 7,475,394
- Issue date Jan 6, 2009
- ARM Limited
- Brad Calder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recovery from errors in a data processing apparatus
- Patent number 7,401,273
- Issue date Jul 15, 2008
- ARM Limited
- Seokwoo Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for reduced-tag dynamic scheduling and reduced-tag predic...
- Patent number 7,398,375
- Issue date Jul 8, 2008
- The Regents of the University of Michigan
- Daniel J. Ernst
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systematic and random error detection and recovery within processin...
- Patent number 7,337,356
- Issue date Feb 26, 2008
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data retention latch provision within integrated circuits
- Patent number 7,310,755
- Issue date Dec 18, 2007
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection and recovery within processing stages of an integra...
- Patent number 7,278,080
- Issue date Oct 2, 2007
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systematic and random error detection and recovery within processin...
- Patent number 7,162,661
- Issue date Jan 9, 2007
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system having fast and slow data reading mechanisms
- Patent number 7,072,229
- Issue date Jul 4, 2006
- ARM Limited
- Todd Michael Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system having fast and slow data reading mechanisms
- Patent number 6,944,067
- Issue date Sep 13, 2005
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
THWARTING CONTROL PLANE ATTACKS WITH DISPLACED AND DILATED ADDRESS...
- Publication number 20220277072
- Publication date Sep 1, 2022
- Regents of the University of Michigan
- Todd Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIVACY-ENHANCED COMPUTATION VIA SEQUESTERED ENCRYPTION
- Publication number 20220198068
- Publication date Jun 23, 2022
- Agita Labs, Inc.
- Todd M. Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIVACY-ENHANCED COMPUTATION VIA SEQUESTERED ENCRYPTION
- Publication number 20220198067
- Publication date Jun 23, 2022
- Agita Labs, Inc.
- Todd M. Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER SYSTEM WITH MOVING TARGET DEFENSES AGAINST VULNERABILITY A...
- Publication number 20220129563
- Publication date Apr 28, 2022
- Regents of the University of Michigan
- Todd Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER SYSTEM WITH MOVING TARGET DEFENSES AGAINST VULNERABILITY A...
- Publication number 20200110884
- Publication date Apr 9, 2020
- The Regents of the University of Michigan
- Todd Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Recovery within Integrated Circuit
- Publication number 20160378588
- Publication date Dec 29, 2016
- ARM Limited
- KRISZTIAN FLAUTNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Recovery Within Integrated Circuit
- Publication number 20160034339
- Publication date Feb 4, 2016
- ARM Limited
- Krisztian FLAUTNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR RECOVERY WITHIN INTEGRATED CIRCUIT
- Publication number 20140181581
- Publication date Jun 26, 2014
- The Regents of the University of Michigan
- Krisztian FLAUTNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR RECOVERY WITHIN INTEGRATED CIRCUIT
- Publication number 20140013178
- Publication date Jan 9, 2014
- The Regents of the University of Michigan
- Krisztian FLAUTNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN
- Publication number 20120011422
- Publication date Jan 12, 2012
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN
- Publication number 20110214014
- Publication date Sep 1, 2011
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error recover within processing stages of an integrated circuit
- Publication number 20110126051
- Publication date May 26, 2011
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error recovery within integrated circuit
- Publication number 20110107166
- Publication date May 5, 2011
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error recovery within processing stages of an integrated circuit
- Publication number 20110093737
- Publication date Apr 21, 2011
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error recovery within processing stages of an integrated circuit
- Publication number 20100058107
- Publication date Mar 4, 2010
- The Regents of the University of Michigan
- David Theodore Blaauw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN
- Publication number 20090138772
- Publication date May 28, 2009
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIELD REPAIRABLE LOGIC
- Publication number 20090089615
- Publication date Apr 2, 2009
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CUSTOMIZED SILICON CHIPS PRODUCED USING DYNAMICALLY CONFIGURABLE PO...
- Publication number 20080164907
- Publication date Jul 10, 2008
- University of Washington
- Martha Mercaldi-Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Error detection and recovery within processing stages of an integra...
- Publication number 20070288798
- Publication date Dec 13, 2007
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit with error correction mechanisms to offset narro...
- Publication number 20060200699
- Publication date Sep 7, 2006
- ARM Limited
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system having fast and slow data reading mechanisms
- Publication number 20060018171
- Publication date Jan 26, 2006
- ARM Limited
- Todd Michael Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Recovery from errors in a data processing apparatus
- Publication number 20050207521
- Publication date Sep 22, 2005
- ARM Limited
- Seokwoo Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of analyzing interpreted programs
- Publication number 20050125777
- Publication date Jun 9, 2005
- Brad Calder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systematic and random error detection and recovery within processin...
- Publication number 20050022094
- Publication date Jan 27, 2005
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data retention latch provision within integrated circuits
- Publication number 20040239397
- Publication date Dec 2, 2004
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systematic and random error detection and recovery within processin...
- Publication number 20040243893
- Publication date Dec 2, 2004
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system having fast and slow data reading mechanisms
- Publication number 20040223386
- Publication date Nov 11, 2004
- ARM Limited
- Trevor Nigel Mudge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error detection and recovery within processing stages of an integra...
- Publication number 20040199821
- Publication date Oct 7, 2004
- Krisztian Flautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for reduced-tag dynamic scheduling
- Publication number 20030191925
- Publication date Oct 9, 2003
- Daniel J. Ernst
- G06 - COMPUTING CALCULATING COUNTING

Todd Michael Austin

Person

Patents Grantslast 30 patents

Privacy-enhanced computation via sequestered encryption

Computer system with moving target defenses against vulnerability a...

Privacy-enhanced computation via sequestered encryption

Computer system with moving target defenses against vulnerability a...

Error recovery within integrated circuit

Error recovery within integrated circuit

Field repairable logic

Error recovery within integrated circuit

Error recovery within integrated circuit

Error recovery within integrated circuit

Error recover within processing stages of an integrated circuit

Microprocessor and method for detecting faults therein

Error recovery within processing stages of an integrated circuit

Error recovery within processing stages of an integrated circuit

Microprocessor and method for detecting faults therein

Microprocessor and method for detecting faults therein

Integrated circuit with error correction mechanisms to offset narro...

Error detection and recovery within processing stages of an integra...

Customized silicon chips produced using dynamically configurable po...

System and method of analyzing interpreted programs

Recovery from errors in a data processing apparatus

Technique for reduced-tag dynamic scheduling and reduced-tag predic...

Systematic and random error detection and recovery within processin...

Data retention latch provision within integrated circuits

Error detection and recovery within processing stages of an integra...

Systematic and random error detection and recovery within processin...

Memory system having fast and slow data reading mechanisms

Memory system having fast and slow data reading mechanisms

Patents Applicationslast 30 patents

THWARTING CONTROL PLANE ATTACKS WITH DISPLACED AND DILATED ADDRESS...

PRIVACY-ENHANCED COMPUTATION VIA SEQUESTERED ENCRYPTION

PRIVACY-ENHANCED COMPUTATION VIA SEQUESTERED ENCRYPTION

COMPUTER SYSTEM WITH MOVING TARGET DEFENSES AGAINST VULNERABILITY A...

COMPUTER SYSTEM WITH MOVING TARGET DEFENSES AGAINST VULNERABILITY A...

Error Recovery within Integrated Circuit

Error Recovery Within Integrated Circuit

ERROR RECOVERY WITHIN INTEGRATED CIRCUIT

ERROR RECOVERY WITHIN INTEGRATED CIRCUIT

MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN

MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN

Error recover within processing stages of an integrated circuit

Error recovery within integrated circuit

Error recovery within processing stages of an integrated circuit

Error recovery within processing stages of an integrated circuit

MICROPROCESSOR AND METHOD FOR DETECTING FAULTS THEREIN

FIELD REPAIRABLE LOGIC

CUSTOMIZED SILICON CHIPS PRODUCED USING DYNAMICALLY CONFIGURABLE PO...

Error detection and recovery within processing stages of an integra...

Integrated circuit with error correction mechanisms to offset narro...

Memory system having fast and slow data reading mechanisms

Recovery from errors in a data processing apparatus

System and method of analyzing interpreted programs

Systematic and random error detection and recovery within processin...

Data retention latch provision within integrated circuits

Systematic and random error detection and recovery within processin...

Memory system having fast and slow data reading mechanisms

Error detection and recovery within processing stages of an integra...

Technique for reduced-tag dynamic scheduling