Tohru Furuyama

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South Burlington, VT, US

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Patents Grantslast 30 patents

Information Patent Grant
Memory circuit with built-in cache memory
- Patent number 5,890,186
- Issue date Mar 30, 1999
- Kabushiki Kaisha Toshiba
- Katsuhiko Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock synchronous type DRAM with latch
- Patent number 5,754,481
- Issue date May 19, 1998
- Kabushiki Kaisha Toshiba
- Tomoaki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock synchronous type DRAM with data latch
- Patent number 5,659,507
- Issue date Aug 19, 1997
- Kabushiki Kaisha Toshiba
- Tomoaki Yabe
- G11 - INFORMATION STORAGE