Tolga Ozguner

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
No miss cache structure for real-time image transformations with mu...
- Patent number 10,672,368
- Issue date Jun 2, 2020
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectively applying reprojection processing to multi-layer scenes...
- Patent number 10,514,753
- Issue date Dec 24, 2019
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- A63 - SPORTS GAMES AMUSEMENTS
Information Patent Grant
Selective application of reprojection processing on layer sub-regio...
- Patent number 10,410,349
- Issue date Sep 10, 2019
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for multistage post-rendering image transformation
- Patent number 10,403,029
- Issue date Sep 3, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-rendering image transformation using parallel image transforma...
- Patent number 10,360,832
- Issue date Jul 23, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing negative effects of insufficient data throughput for real-...
- Patent number 10,338,816
- Issue date Jul 2, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No miss cache structure for real-time image transformations with mu...
- Patent number 10,255,891
- Issue date Apr 9, 2019
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No miss cache structure for real-time image transformations with da...
- Patent number 10,241,470
- Issue date Mar 26, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No miss cache structure for real-time image transformations
- Patent number 10,242,654
- Issue date Mar 26, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing negative effects of insufficient data throughput for real-...
- Patent number 10,095,408
- Issue date Oct 9, 2018
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No miss cache structure for real-time image transformations with da...
- Patent number 9,978,118
- Issue date May 22, 2018
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Interrupt controller
- Patent number 9,747,225
- Issue date Aug 29, 2017
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller to utilize DRAM write buffers
- Patent number 8,219,745
- Issue date Jul 10, 2012
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for indexing memory of a network processor
- Patent number 8,213,428
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Gerald G. Fagerness
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Implementing pointer and stake model for frame alteration code in a...
- Patent number 8,170,024
- Issue date May 1, 2012
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reuse of functional data buffers for pattern buffers in XDR DRAM
- Patent number 7,925,823
- Issue date Apr 12, 2011
- International Business Machines Corporation
- Mark David Bellows
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller operating in a system with a variable system clock
- Patent number 7,761,682
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Melissa Ann Barnum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory command and address conversion between an XDR interface and...
- Patent number 7,757,040
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Mark D. Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing conditional packet alterations based on transmit port
- Patent number 7,757,006
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Managing write-to-read turnarounds in an early read after write mem...
- Patent number 7,752,379
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing data bandwidth across a variable asynchronous clock domain
- Patent number 7,669,028
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Mark D. Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing write-to-read turnarounds in an early read after write mem...
- Patent number 7,487,318
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing conditional packet alterations based on transmit port
- Patent number 7,475,161
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory controller operating in a system with a variable system clock
- Patent number 7,467,277
- Issue date Dec 16, 2008
- International Business Machines Corporation
- Melissa Ann Barnum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of functional data buffers for pattern buffers in XDR DRAM
- Patent number 7,380,052
- Issue date May 27, 2008
- International Business Machines Corporation
- Mark David Bellows
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and computer program product for implementing po...
- Patent number 7,330,478
- Issue date Feb 12, 2008
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for managing write-to-read turnarounds in an e...
- Patent number 7,321,950
- Issue date Jan 22, 2008
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing alterations on multiple concu...
- Patent number 7,239,635
- Issue date Jul 3, 2007
- International Business Machines Corporation
- Tolga Ozguner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for implementing frame header alterations usin...
- Patent number 7,224,701
- Issue date May 29, 2007
- International Business Machines Corporation
- Tolga Ozguner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for memory calibration
- Patent number 7,225,097
- Issue date May 29, 2007
- International Business Machines Corporation
- Paul A. Ganfield
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
No Miss Cache Structure for Real-Time Image Transformations with Mu...
- Publication number 20190189089
- Publication date Jun 20, 2019
- Microsoft Technology Licensing, LLC
- Ryan Scott HARADEN
- G02 - OPTICS
Information Patent Application
REDUCING NEGATIVE EFFECTS OF INSUFFICIENT DATA THROUGHPUT FOR REAL-...
- Publication number 20190050149
- Publication date Feb 14, 2019
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-RENDERING IMAGE TRANSFORMATION USING PARALLEL IMAGE TRANSFORMA...
- Publication number 20190051229
- Publication date Feb 14, 2019
- Microsoft Technology Licensing, LLC
- Tolga OZGUNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR MULTISTAGE POST-RENDERING IMAGE TRANSFORMATION
- Publication number 20180322688
- Publication date Nov 8, 2018
- Microsoft Technology Licensing, LLC
- Tolga OZGUNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
No Miss Cache Structure for Real-Time Image Transformations with Mu...
- Publication number 20180301125
- Publication date Oct 18, 2018
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE APPLICATION OF REPROJECTION PROCESSING ON LAYER SUB-REGIO...
- Publication number 20180276824
- Publication date Sep 27, 2018
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVELY APPLYING REPROJECTION PROCESSING TO MULTI-LAYER SCENES...
- Publication number 20180275748
- Publication date Sep 27, 2018
- Microsoft Technology Licensing, LLC
- Ryan Scott Haraden
- A63 - SPORTS GAMES AMUSEMENTS
Information Patent Application
REDUCING NEGATIVE EFFECTS OF INSUFFICENT DATA THROUGHPUT FOR REAL-T...
- Publication number 20180260120
- Publication date Sep 13, 2018
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
No Miss Cache Structure for Real-Time Image Transformations with Da...
- Publication number 20180260931
- Publication date Sep 13, 2018
- Microsoft Technology Licensing, LLC
- Tolga OZGUNER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
No Miss Cache Structure for Real-Time Image Transformations
- Publication number 20180211638
- Publication date Jul 26, 2018
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPT CONTROLLER
- Publication number 20160328339
- Publication date Nov 10, 2016
- Microsoft Technology Licensing, LLC
- Tolga Ozguner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT
- Publication number 20090144452
- Publication date Jun 4, 2009
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Managing Write-to-Read Turnarounds in an Early Read After Write Mem...
- Publication number 20090119442
- Publication date May 7, 2009
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK
- Publication number 20080307184
- Publication date Dec 11, 2008
- Melissa Ann Barnum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Command and Address Conversion Between an XDR Interface and...
- Publication number 20080183925
- Publication date Jul 31, 2008
- International Business Machines Corporation
- Mark D. Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Extreme Data Rate Memory Commands to Scrub and Refresh Double...
- Publication number 20080183916
- Publication date Jul 31, 2008
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Software Control of a Non-Functional Oper...
- Publication number 20080168262
- Publication date Jul 10, 2008
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces
- Publication number 20080168298
- Publication date Jul 10, 2008
- Mark David Bellows
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and Apparatus for Interfacing a Processor and a Memory
- Publication number 20080168206
- Publication date Jul 10, 2008
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING PO...
- Publication number 20080063009
- Publication date Mar 13, 2008
- International Business Machines
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and Apparatus for Managing Write-to-Read Turnarounds in an E...
- Publication number 20080046632
- Publication date Feb 21, 2008
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reuse of Functional Data Buffers for Pattern Buffers in XDR DRAM
- Publication number 20080040534
- Publication date Feb 14, 2008
- Mark David Bellows
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for guaranteeing memory bandwidth for trace data
- Publication number 20070220361
- Publication date Sep 20, 2007
- International Business Machines Corporation
- Melissa A. Barnum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller operating in a system with a variable system clock
- Publication number 20070183192
- Publication date Aug 9, 2007
- International Business Machines Corporation
- Melissa Ann Barnum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing data bandwidth across a variable asynchronous clock domain
- Publication number 20070186071
- Publication date Aug 9, 2007
- International Business Machines Corporation
- Mark D. Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for memory calibration
- Publication number 20070027650
- Publication date Feb 1, 2007
- International Business Machines Corporation
- Paul A. Ganfield
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for managing write-to-read turnarounds in an e...
- Publication number 20060174082
- Publication date Aug 3, 2006
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reuse of functional data buffers for pattern buffers in XDR DRAM
- Publication number 20060129754
- Publication date Jun 15, 2006
- International Business Machines Corporation
- Mark David Bellows
- G11 - INFORMATION STORAGE
Information Patent Application
Memory controller to utilize DRAM write buffers
- Publication number 20060123187
- Publication date Jun 8, 2006
- International Business Machines Corporation
- Mark David Bellows
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and computer program product for implementing po...
- Publication number 20050063415
- Publication date Mar 24, 2005
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Tolga Ozguner

Person

Patents Grantslast 30 patents

No miss cache structure for real-time image transformations with mu...

Selectively applying reprojection processing to multi-layer scenes...

Selective application of reprojection processing on layer sub-regio...

Methods and systems for multistage post-rendering image transformation

Post-rendering image transformation using parallel image transforma...

Reducing negative effects of insufficient data throughput for real-...

No miss cache structure for real-time image transformations with mu...

No miss cache structure for real-time image transformations with da...

No miss cache structure for real-time image transformations

Reducing negative effects of insufficient data throughput for real-...

No miss cache structure for real-time image transformations with da...

Interrupt controller

Memory controller to utilize DRAM write buffers

Methods and apparatus for indexing memory of a network processor

Implementing pointer and stake model for frame alteration code in a...

Reuse of functional data buffers for pattern buffers in XDR DRAM

Memory controller operating in a system with a variable system clock

Memory command and address conversion between an XDR interface and...

Implementing conditional packet alterations based on transmit port

Managing write-to-read turnarounds in an early read after write mem...

Optimizing data bandwidth across a variable asynchronous clock domain

Managing write-to-read turnarounds in an early read after write mem...

Implementing conditional packet alterations based on transmit port

Memory controller operating in a system with a variable system clock

Reuse of functional data buffers for pattern buffers in XDR DRAM

Method, apparatus, and computer program product for implementing po...

Method and apparatus for managing write-to-read turnarounds in an e...

Method and apparatus for implementing alterations on multiple concu...

Method and apparatus for implementing frame header alterations usin...

Methods and apparatus for memory calibration

Patents Applicationslast 30 patents

No Miss Cache Structure for Real-Time Image Transformations with Mu...

REDUCING NEGATIVE EFFECTS OF INSUFFICIENT DATA THROUGHPUT FOR REAL-...

POST-RENDERING IMAGE TRANSFORMATION USING PARALLEL IMAGE TRANSFORMA...

METHODS AND SYSTEMS FOR MULTISTAGE POST-RENDERING IMAGE TRANSFORMATION

No Miss Cache Structure for Real-Time Image Transformations with Mu...

SELECTIVE APPLICATION OF REPROJECTION PROCESSING ON LAYER SUB-REGIO...

SELECTIVELY APPLYING REPROJECTION PROCESSING TO MULTI-LAYER SCENES...

REDUCING NEGATIVE EFFECTS OF INSUFFICENT DATA THROUGHPUT FOR REAL-T...

No Miss Cache Structure for Real-Time Image Transformations with Da...

No Miss Cache Structure for Real-Time Image Transformations

INTERRUPT CONTROLLER

IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT

Managing Write-to-Read Turnarounds in an Early Read After Write Mem...

MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK

Memory Command and Address Conversion Between an XDR Interface and...

Using Extreme Data Rate Memory Commands to Scrub and Refresh Double...

Methods and Apparatus for Software Control of a Non-Functional Oper...

Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces

Methods and Apparatus for Interfacing a Processor and a Memory

METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING PO...

Method and Apparatus for Managing Write-to-Read Turnarounds in an E...

Reuse of Functional Data Buffers for Pattern Buffers in XDR DRAM

Method and apparatus for guaranteeing memory bandwidth for trace data

Memory controller operating in a system with a variable system clock

Optimizing data bandwidth across a variable asynchronous clock domain

Methods and apparatus for memory calibration

Method and apparatus for managing write-to-read turnarounds in an e...

Reuse of functional data buffers for pattern buffers in XDR DRAM

Memory controller to utilize DRAM write buffers

Method, apparatus, and computer program product for implementing po...