Tom Fletcher

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 12,073,214
- Issue date Aug 27, 2024
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 11,487,541
- Issue date Nov 1, 2022
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 10,853,065
- Issue date Dec 1, 2020
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 10,146,535
- Issue date Dec 4, 2018
- Intel Corporatoin
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector mask driven clock gating for power efficiency of a processor
- Patent number 10,133,577
- Issue date Nov 20, 2018
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Super multiply add (super MADD) instructions with three scalar terms
- Patent number 9,792,115
- Issue date Oct 17, 2017
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to provide vector linear interpolation functi...
- Patent number 9,766,886
- Issue date Sep 19, 2017
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Super multiply add (super madd) instruction
- Patent number 9,733,935
- Issue date Aug 15, 2017
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consecutive bit error detection and correction
- Patent number 9,654,143
- Issue date May 16, 2017
- Intel Corporation
- Guillem Sole
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Functional unit capable of executing approximations of functions
- Patent number 9,639,355
- Issue date May 2, 2017
- Intel Corporation
- Alex Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for multiplier selectors for merging math fun...
- Patent number 9,588,765
- Issue date Mar 7, 2017
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Math circuit for estimating a transcendental function
- Patent number 9,465,580
- Issue date Oct 11, 2016
- Intel Corporation
- Jose-Alejandro Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit respo...
- Patent number 9,323,500
- Issue date Apr 26, 2016
- Intel Corporation
- Brian Hickmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit respo...
- Patent number 9,152,382
- Issue date Oct 6, 2015
- Intel Corporation
- Brian J. Hickmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method, apparatus, system for single-path floating-point rounding f...
- Patent number 9,141,586
- Issue date Sep 22, 2015
- Intel Corporation
- Warren E. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having execution core sections operating at different clo...
- Patent number RE45487
- Issue date Apr 21, 2015
- Intel Corporation
- David J. Sager
- 713 - Electrical computers and digital processing systems: support
Information Patent Grant
Functional unit capable of executing approximations of functions
- Patent number 8,676,871
- Issue date Mar 18, 2014
- Intel Corporation
- Alex Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having execution core sections operating at different clo...
- Patent number RE44494
- Issue date Sep 10, 2013
- Intel Corporation
- David J. Sager
- 713 - Electrical computers and digital processing systems: support
Information Patent Grant
Partially gated mux-latch keeper
- Patent number 7,436,220
- Issue date Oct 14, 2008
- Intel Corporation
- Kumar A Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Symmetric cascaded domino carry generate circuit
- Patent number 7,428,568
- Issue date Sep 23, 2008
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascaded domino four-to-two reducer circuit and method
- Patent number 7,392,277
- Issue date Jun 24, 2008
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-ahead carry adder circuit
- Patent number 7,325,025
- Issue date Jan 29, 2008
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart buffer circuit to match a delay over a range of loads
- Patent number 7,009,437
- Issue date Mar 7, 2006
- Intel Corporation
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multistage clock delay circuit and method
- Patent number 6,928,572
- Issue date Aug 9, 2005
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data-enabled static flip-flop circuit with no extra forward-path de...
- Patent number 6,864,733
- Issue date Mar 8, 2005
- Intel Corporation
- Kumar Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vectored flip-flops and latches with embedded output-merge logic an...
- Patent number 6,828,838
- Issue date Dec 7, 2004
- Intel Corporation
- Kumar A. Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential sense latch scheme
- Patent number 6,756,823
- Issue date Jun 29, 2004
- Intel Corporation
- Feng Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for correcting a clock duty cycle in a clock d...
- Patent number 6,750,689
- Issue date Jun 15, 2004
- Intel Corporation
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential, low voltage swing reducer
- Patent number 6,732,136
- Issue date May 4, 2004
- Intel Corporation
- Feng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed clock signal transfer circuits with dynamic latching
- Patent number 6,667,645
- Issue date Dec 23, 2003
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20230083705
- Publication date Mar 16, 2023
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20210081198
- Publication date Mar 18, 2021
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20190121637
- Publication date Apr 25, 2019
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20180113708
- Publication date Apr 26, 2018
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC TO PROVIDE VECTOR LINEAR INTERPOLATION FUNCTI...
- Publication number 20160266902
- Publication date Sep 15, 2016
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR MULTIPLIER SELECTORS FOR MERGING MATH FUN...
- Publication number 20160092215
- Publication date Mar 31, 2016
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSECUTIVE BIT ERROR DETECTION AND CORRECTION
- Publication number 20150370636
- Publication date Dec 24, 2015
- Guillem Sole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR
- Publication number 20150220345
- Publication date Aug 6, 2015
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION
- Publication number 20140222883
- Publication date Aug 7, 2014
- Jose-Alejandro Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS
- Publication number 20140201504
- Publication date Jul 17, 2014
- Alex Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, SYSTEM FOR SINGLE-PATH FLOATING-POINT ROUNDING F...
- Publication number 20140181169
- Publication date Jun 26, 2014
- WARREN E. FERGUSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT RESPO...
- Publication number 20140122555
- Publication date May 1, 2014
- BRIAN HICKMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Power Consumption In A Fused Multiply-Add (FMA) Unit Respo...
- Publication number 20140122554
- Publication date May 1, 2014
- Brian J. Hickmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION
- Publication number 20140052968
- Publication date Feb 20, 2014
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTIONS WITH THREE SCALAR TERMS
- Publication number 20140052969
- Publication date Feb 20, 2014
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS
- Publication number 20120079250
- Publication date Mar 29, 2012
- Alex Pineiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLO...
- Publication number 20120042151
- Publication date Feb 16, 2012
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partially gated mux-latch keeper
- Publication number 20070240094
- Publication date Oct 11, 2007
- Kumar A. Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Register file cache
- Publication number 20050138297
- Publication date Jun 23, 2005
- Intel Corporation
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTORED FLIP-FLOPS AND LATCHES WITH EMBEDDED OUTPUT-MERGE LOGIC AN...
- Publication number 20040239392
- Publication date Dec 2, 2004
- Intel Corporation
- Kumar A. Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data-enabled static flip-flop circuit with no extra forward-path de...
- Publication number 20040239393
- Publication date Dec 2, 2004
- Intel Corporation
- Kumar Anshumali
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Smart buffer circuit to match a delay over a range of loads
- Publication number 20040217792
- Publication date Nov 4, 2004
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interconnect structure including write and read structures
- Publication number 20040123037
- Publication date Jun 24, 2004
- Wilfred Gomes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric cascaded domino carry generate circuit
- Publication number 20030126179
- Publication date Jul 3, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Look-ahead carry adder circuit
- Publication number 20030115237
- Publication date Jun 19, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS
- Publication number 20030112036
- Publication date Jun 19, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cascaded domino four-to-two reducer circuit and method
- Publication number 20030014459
- Publication date Jan 16, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multistage clock delay circuit and method
- Publication number 20030005345
- Publication date Jan 2, 2003
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric differential domino "AND gate"
- Publication number 20030001622
- Publication date Jan 2, 2003
- Thomas Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for correcting a clock duty cycle
- Publication number 20020140478
- Publication date Oct 3, 2002
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY

Tom Fletcher

Person

Patents Grantslast 30 patents

Systems, apparatuses, and methods for chained fused multiply add

Systems, apparatuses, and methods for chained fused multiply add

Systems, apparatuses, and methods for chained fused multiply add

Systems, apparatuses, and methods for chained fused multiply add

Vector mask driven clock gating for power efficiency of a processor

Super multiply add (super MADD) instructions with three scalar terms

Instruction and logic to provide vector linear interpolation functi...

Super multiply add (super madd) instruction

Consecutive bit error detection and correction

Functional unit capable of executing approximations of functions

Instruction and logic for multiplier selectors for merging math fun...

Math circuit for estimating a transcendental function

Reducing power consumption in a fused multiply-add (FMA) unit respo...

Reducing power consumption in a fused multiply-add (FMA) unit respo...

Method, apparatus, system for single-path floating-point rounding f...

Processor having execution core sections operating at different clo...

Functional unit capable of executing approximations of functions

Processor having execution core sections operating at different clo...

Partially gated mux-latch keeper

Symmetric cascaded domino carry generate circuit

Cascaded domino four-to-two reducer circuit and method

Look-ahead carry adder circuit

Smart buffer circuit to match a delay over a range of loads

Multistage clock delay circuit and method

Data-enabled static flip-flop circuit with no extra forward-path de...

Vectored flip-flops and latches with embedded output-merge logic an...

Differential sense latch scheme

Method and apparatus for correcting a clock duty cycle in a clock d...

Differential, low voltage swing reducer

Pulsed clock signal transfer circuits with dynamic latching

Patents Applicationslast 30 patents

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

INSTRUCTION AND LOGIC TO PROVIDE VECTOR LINEAR INTERPOLATION FUNCTI...

INSTRUCTION AND LOGIC FOR MULTIPLIER SELECTORS FOR MERGING MATH FUN...

CONSECUTIVE BIT ERROR DETECTION AND CORRECTION

VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR

MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION

FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS

METHOD, APPARATUS, SYSTEM FOR SINGLE-PATH FLOATING-POINT ROUNDING F...

REDUCING POWER CONSUMPTION IN A FUSED MULTIPLY-ADD (FMA) UNIT RESPO...

Reducing Power Consumption In A Fused Multiply-Add (FMA) Unit Respo...

SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION

SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTIONS WITH THREE SCALAR TERMS

FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS

PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLO...

Partially gated mux-latch keeper

Register file cache

VECTORED FLIP-FLOPS AND LATCHES WITH EMBEDDED OUTPUT-MERGE LOGIC AN...

Data-enabled static flip-flop circuit with no extra forward-path de...

Smart buffer circuit to match a delay over a range of loads

Interconnect structure including write and read structures

Symmetric cascaded domino carry generate circuit

Look-ahead carry adder circuit

ZIPPER DOMINO CARRY GENERATE CELL FOR FAST ADDERS

Cascaded domino four-to-two reducer circuit and method

Multistage clock delay circuit and method

Symmetric differential domino "AND gate"

Method and apparatus for correcting a clock duty cycle