Tomai Knopp

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock and phase alignment between physical layers and controller
- Patent number 11,581,881
- Issue date Feb 14, 2023
- Xilinx, Inc.
- Sarosh I. Azad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and circuits for deadlock avoidance
- Patent number 11,281,618
- Issue date Mar 22, 2022
- XLNX, INC.
- Sagheer Ahmad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory repair network
- Patent number 10,861,578
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Roger D. Flateau
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-destructive online testing for safety critical applications
- Patent number 10,169,177
- Issue date Jan 1, 2019
- Xilinx, Inc.
- Banadappa V Shivaray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement with transaction timeout detection
- Patent number 10,042,692
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Sarosh I. Azad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-configurable error handling
- Patent number 9,495,239
- Issue date Nov 15, 2016
- Xilinx, Inc.
- Sagheer Ahmad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolation interface for master-slave communication protocols
- Patent number 9,465,766
- Issue date Oct 11, 2016
- Xilinx, Inc.
- Tomai Knopp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for and method of realigning data at a receiver
- Patent number 9,348,750
- Issue date May 24, 2016
- Xilinx, Inc.
- Tomai Knopp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deadlock-resistant bus bridge with pipeline-restricted address ranges
- Patent number 7,970,977
- Issue date Jun 28, 2011
- Xilinx, Inc.
- Kam-Wing Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method of transmitting a block of data
- Patent number 7,539,923
- Issue date May 26, 2009
- Xilinx, Inc.
- Tomai Knopp
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CLOCK AND PHASE ALIGNMENT BETWEEN PHYSICAL LAYERS AND CONTROLLER
- Publication number 20230059517
- Publication date Feb 23, 2023
- Xilinx, Inc.
- Sarosh I. AZAD
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND CIRCUITS FOR DEADLOCK AVOIDANCE
- Publication number 20160124891
- Publication date May 5, 2016
- Xilinx, Inc.
- Sagheer Ahmad
- G06 - COMPUTING CALCULATING COUNTING

Tomai Knopp

Person

Patents Grantslast 30 patents

Clock and phase alignment between physical layers and controller

Methods and circuits for deadlock avoidance

Distributed memory repair network

Non-destructive online testing for safety critical applications

Circuit arrangement with transaction timeout detection

User-configurable error handling

Isolation interface for master-slave communication protocols

Circuit for and method of realigning data at a receiver

Deadlock-resistant bus bridge with pipeline-restricted address ranges

Circuit and method of transmitting a block of data

Patents Applicationslast 30 patents

CLOCK AND PHASE ALIGNMENT BETWEEN PHYSICAL LAYERS AND CONTROLLER

METHODS AND CIRCUITS FOR DEADLOCK AVOIDANCE