Tomasz Czajkowski

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for dynamically simplifying processor instruct...
- Patent number 11,816,488
- Issue date Nov 14, 2023
- Huawei Technologies Co., Ltd.
- Henry Fangli Kao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for functional unit balancing at program compi...
- Patent number 11,755,299
- Issue date Sep 12, 2023
- Huawei Technologies Co., Ltd.
- Tomasz S. Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-size- and bandwidth-efficient method for feeding systolic ar...
- Patent number 11,328,037
- Issue date May 10, 2022
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Toggle rate reduction in high level programming implementations
- Patent number 11,256,836
- Issue date Feb 22, 2022
- Intel Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
M/A for compiling parallel program having barrier synchronization f...
- Patent number 10,599,404
- Issue date Mar 24, 2020
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product based processing elements
- Patent number 10,339,201
- Issue date Jul 2, 2019
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product based processing elements
- Patent number 10,049,082
- Issue date Aug 14, 2018
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double-precision floating-point operation
- Patent number 10,007,487
- Issue date Jun 26, 2018
- Altera Corporation
- Tomasz Sebastian Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused floating-point arithmetic circuitry
- Patent number 9,904,514
- Issue date Feb 27, 2018
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fixed-point and floating-point optimization
- Patent number 9,696,991
- Issue date Jul 4, 2017
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating-point adder circuitry
- Patent number 9,639,326
- Issue date May 2, 2017
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repartitioning and reordering of multiple threads into subsets base...
- Patent number 9,626,218
- Issue date Apr 18, 2017
- Altera Corporation
- Dmitry Denisenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cycle resource sharing
- Patent number 9,430,425
- Issue date Aug 30, 2016
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward-flow selection
- Patent number 9,424,043
- Issue date Aug 23, 2016
- Altera Corporation
- John Stuart Freeman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating-point adder circuitry
- Patent number 9,405,728
- Issue date Aug 2, 2016
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for performing dynamic data alignment for flo...
- Patent number 9,400,635
- Issue date Jul 26, 2016
- Altera Corporation
- Tomasz Sebastian Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Workgroup handling in pipelined circuits
- Patent number 9,135,087
- Issue date Sep 15, 2015
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF PREFETCHING ARRAY SEGMENTS
- Publication number 20240012646
- Publication date Jan 11, 2024
- Huawei Technologies Co., Ltd
- Tomasz Sebastian CZAJKOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20230359695
- Publication date Nov 9, 2023
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DYNAMIC INSTRUCTION SIMPLIFICATION BASED ON REGISTER VA...
- Publication number 20230145754
- Publication date May 11, 2023
- Huawei Technologies Co., Ltd
- Henry Fangli KAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20230064381
- Publication date Mar 2, 2023
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR FUNCTIONAL UNIT BALANCING AT PROGRAM COMPI...
- Publication number 20220413818
- Publication date Dec 29, 2022
- Huawei Technologies Co., Ltd
- Tomasz S. Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOGGLE RATE REDUCTION IN HIGH LEVEL PROGRAMMING IMPLEMENTATIONS
- Publication number 20190042673
- Publication date Feb 7, 2019
- Intel Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20190012295
- Publication date Jan 10, 2019
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOT PRODUCT BASED PROCESSING ELEMENTS
- Publication number 20180074996
- Publication date Mar 15, 2018
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT ADDER CIRCUITRY
- Publication number 20160291934
- Publication date Oct 6, 2016
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT ADDER CIRCUITRY
- Publication number 20150067010
- Publication date Mar 5, 2015
- Altera Corporation
- Tomasz Czajkowski
- G06 - COMPUTING CALCULATING COUNTING

Tomasz Czajkowski

Person

Patents Grantslast 30 patents

Method and apparatus for dynamically simplifying processor instruct...

Method and apparatus for functional unit balancing at program compi...

Memory-size- and bandwidth-efficient method for feeding systolic ar...

Toggle rate reduction in high level programming implementations

M/A for compiling parallel program having barrier synchronization f...

Dot product based processing elements

Dot product based processing elements

Double-precision floating-point operation

Fused floating-point arithmetic circuitry

Fixed-point and floating-point optimization

Floating-point adder circuitry

Repartitioning and reordering of multiple threads into subsets base...

Multi-cycle resource sharing

Forward-flow selection

Floating-point adder circuitry

Methods and apparatus for performing dynamic data alignment for flo...

Workgroup handling in pipelined circuits

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF PREFETCHING ARRAY SEGMENTS

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

METHODS FOR DYNAMIC INSTRUCTION SIMPLIFICATION BASED ON REGISTER VA...

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

METHOD AND APPARATUS FOR FUNCTIONAL UNIT BALANCING AT PROGRAM COMPI...

TOGGLE RATE REDUCTION IN HIGH LEVEL PROGRAMMING IMPLEMENTATIONS

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

DOT PRODUCT BASED PROCESSING ELEMENTS

FLOATING-POINT ADDER CIRCUITRY

FLOATING-POINT ADDER CIRCUITRY