Tomoko Ogura

Person

Fishkill, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Complementary reference method for high reliability trap-type non-v...
- Patent number 9,123,419
- Issue date Sep 1, 2015
- Halo LSI, Inc.
- Nori Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin MONOS array for high speed application
- Patent number 8,633,544
- Issue date Jan 21, 2014
- Halo LSI, Inc.
- Kimihiro Satoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Complementary reference method for high reliability trap-type non-v...
- Patent number 8,325,542
- Issue date Dec 4, 2012
- Halo LSI Inc.
- Nori Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed operation method for twin MONOS metal bit array
- Patent number 8,174,885
- Issue date May 8, 2012
- Halo LSI Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Trap-charge non-volatile switch connector for programmable logic
- Patent number 8,139,410
- Issue date Mar 20, 2012
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Trap-charge non-volatile switch connector for programmable logic
- Patent number 8,089,809
- Issue date Jan 3, 2012
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Trap-charge non-volatile switch connector for programmable logic
- Patent number 8,027,198
- Issue date Sep 27, 2011
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Trap-charge non-volatile switch connector for programmable logic
- Patent number 8,023,326
- Issue date Sep 20, 2011
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed operation method for twin MONOS metal bit array
- Patent number 7,936,604
- Issue date May 3, 2011
- Halo LSI Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Trap-charge non-volatile switch connector for programmable logic
- Patent number 7,742,336
- Issue date Jun 22, 2010
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Referencing scheme for trap memory
- Patent number 7,447,077
- Issue date Nov 4, 2008
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin MONOS array for high speed application
- Patent number 7,352,033
- Issue date Apr 1, 2008
- Halo LSI Inc.
- Kimihiro Satoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory array organization and usage
- Patent number 7,190,603
- Issue date Mar 13, 2007
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for making and programming and operating a dual-bit multi-l...
- Patent number 7,149,126
- Issue date Dec 12, 2006
- New Halo, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Stitch and select implementation in twin MONOS array
- Patent number 7,118,961
- Issue date Oct 10, 2006
- Halo LSI, Inc.
- Tomoko Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fast program to program verify method
- Patent number 7,046,553
- Issue date May 16, 2006
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory and driving method
- Patent number 7,031,192
- Issue date Apr 18, 2006
- Halo LSI, Inc.
- Ki-Tae Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Array architecture and operation methods for a nonvolatile memory
- Patent number 7,006,378
- Issue date Feb 28, 2006
- Halo LSI, Inc.
- Tomoya Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of sense and program verify without a reference cell for non...
- Patent number 6,999,345
- Issue date Feb 14, 2006
- Halo LSI, Inc.
- Ki-Tae Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin NAND device structure, array operations and fabrication method
- Patent number 6,998,658
- Issue date Feb 14, 2006
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
High efficiency triple well charge pump circuit
- Patent number 6,914,791
- Issue date Jul 5, 2005
- Halo LSI, Inc.
- Ki-Tae Park
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Fast program to program verify method
- Patent number 6,856,545
- Issue date Feb 15, 2005
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin NAND device structure, array operations and fabrication method
- Patent number 6,825,084
- Issue date Nov 30, 2004
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast program to program verify method
- Patent number 6,807,105
- Issue date Oct 19, 2004
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Stitch and select implementation in twin MONOS array
- Patent number 6,759,290
- Issue date Jul 6, 2004
- Halo LSI, Inc.
- Tomoko Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making and programming and operating a dual-bit multi-l...
- Patent number 6,714,456
- Issue date Mar 30, 2004
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-bit multi-level ballistic MONOS memory
- Patent number 6,686,632
- Issue date Feb 3, 2004
- New Halo, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin NAND device structure, array operations and fabrication method
- Patent number 6,670,240
- Issue date Dec 30, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line decoding scheme and circuit for dual bit memory with a dua...
- Patent number 6,643,172
- Issue date Nov 4, 2003
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Control gate decoder for twin MONOS memory with two bit erase capab...
- Patent number 6,636,438
- Issue date Oct 21, 2003
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Twin MONOS Array for High Speed Application
- Publication number 20140133245
- Publication date May 15, 2014
- HALO LSI, INC.
- Kimihiro Satoh
- G11 - INFORMATION STORAGE
Information Patent Application
Twin MONOS Array for High Speed Application
- Publication number 20140133244
- Publication date May 15, 2014
- HALO LSI, INC.
- Kimihiro Satoh
- G11 - INFORMATION STORAGE
Information Patent Application
Complementary Reference Method for High Reliability Trap-Type Non-V...
- Publication number 20130094299
- Publication date Apr 18, 2013
- HALO LSI, INC.
- Nori Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Complementary Reference Method for High Reliability Trap-Type Non-V...
- Publication number 20130094303
- Publication date Apr 18, 2013
- HALO LSI, INC.
- Nori Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
High speed operation method for Twin MONOS metal bit array
- Publication number 20110205798
- Publication date Aug 25, 2011
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Trap-charge non-volatile switch connector for programmable logic
- Publication number 20100259981
- Publication date Oct 14, 2010
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Trap-charge non-volatile switch connector for programmable logic
- Publication number 20100259985
- Publication date Oct 14, 2010
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Trap-charge non-volatile switch connector for programmable logic
- Publication number 20100261324
- Publication date Oct 14, 2010
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Trap-charge non-volatile switch connector for programmable logic
- Publication number 20100259986
- Publication date Oct 14, 2010
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Complementary Reference method for high reliability trap-type non-v...
- Publication number 20100046302
- Publication date Feb 25, 2010
- Halo LSI, Inc.
- Nori Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Trap-charge non-volatile switch connector for programmable logic
- Publication number 20080101117
- Publication date May 1, 2008
- Gumbo Logic, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
High speed operation method for twin MONOS metal bit array
- Publication number 20070047307
- Publication date Mar 1, 2007
- HALO LSI INC.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Twin MONOS array for high speed application
- Publication number 20070047309
- Publication date Mar 1, 2007
- HALO LSI INC.
- Kimihiro Satoh
- G11 - INFORMATION STORAGE
Information Patent Application
Referencing scheme for trap memory
- Publication number 20070030745
- Publication date Feb 8, 2007
- HALO LSI INC.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile memory array organization and usage
- Publication number 20050248984
- Publication date Nov 10, 2005
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Process for making and programming and operating a dual-bit multi-l...
- Publication number 20050111279
- Publication date May 26, 2005
- New Halo, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Stitch and select implementation in twin MONOS array
- Publication number 20040166630
- Publication date Aug 26, 2004
- Halo LSI, Inc.
- Tomoko Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Twin NAND device structure, array operations and fabrication method
- Publication number 20040092066
- Publication date May 13, 2004
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Twin NAND device structure, array operations and fabrication method
- Publication number 20040087087
- Publication date May 6, 2004
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030185053
- Publication date Oct 2, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030128588
- Publication date Jul 10, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030123291
- Publication date Jul 3, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030123308
- Publication date Jul 3, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030123292
- Publication date Jul 3, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030123290
- Publication date Jul 3, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Fast program to program verify method
- Publication number 20030123293
- Publication date Jul 3, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Control gate decoder for twin MONOS memory with two bit erase capab...
- Publication number 20030079540
- Publication date May 1, 2003
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Bit line decoding scheme and circuit for dual bit memory with a dua...
- Publication number 20030031048
- Publication date Feb 13, 2003
- Halo LSI, Inc.
- Tomoko Ogura
- G11 - INFORMATION STORAGE
Information Patent Application
Twin NAND device structure, array operations and fabrication method
- Publication number 20030032243
- Publication date Feb 13, 2003
- Seiki Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Twin MONOS array metal bit organization and single cell operation
- Publication number 20030022441
- Publication date Jan 30, 2003
- Halo LSI, Inc.
- Seiki Ogura
- G11 - INFORMATION STORAGE

Tomoko Ogura

Person

Patents Grantslast 30 patents

Complementary reference method for high reliability trap-type non-v...

Twin MONOS array for high speed application

Complementary reference method for high reliability trap-type non-v...

High speed operation method for twin MONOS metal bit array

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

High speed operation method for twin MONOS metal bit array

Trap-charge non-volatile switch connector for programmable logic

Referencing scheme for trap memory

Twin MONOS array for high speed application

Nonvolatile memory array organization and usage

Process for making and programming and operating a dual-bit multi-l...

Stitch and select implementation in twin MONOS array

Fast program to program verify method

Non-volatile semiconductor memory and driving method

Array architecture and operation methods for a nonvolatile memory

Method of sense and program verify without a reference cell for non...

Twin NAND device structure, array operations and fabrication method

High efficiency triple well charge pump circuit

Fast program to program verify method

Twin NAND device structure, array operations and fabrication method

Fast program to program verify method

Stitch and select implementation in twin MONOS array

Process for making and programming and operating a dual-bit multi-l...

Dual-bit multi-level ballistic MONOS memory

Twin NAND device structure, array operations and fabrication method

Bit line decoding scheme and circuit for dual bit memory with a dua...

Control gate decoder for twin MONOS memory with two bit erase capab...

Patents Applicationslast 30 patents

Twin MONOS Array for High Speed Application

Twin MONOS Array for High Speed Application

Complementary Reference Method for High Reliability Trap-Type Non-V...

Complementary Reference Method for High Reliability Trap-Type Non-V...

High speed operation method for Twin MONOS metal bit array

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

Trap-charge non-volatile switch connector for programmable logic

Complementary Reference method for high reliability trap-type non-v...

Trap-charge non-volatile switch connector for programmable logic

High speed operation method for twin MONOS metal bit array

Twin MONOS array for high speed application

Referencing scheme for trap memory

Nonvolatile memory array organization and usage

Process for making and programming and operating a dual-bit multi-l...

Stitch and select implementation in twin MONOS array

Twin NAND device structure, array operations and fabrication method

Twin NAND device structure, array operations and fabrication method

Fast program to program verify method

Fast program to program verify method

Fast program to program verify method

Fast program to program verify method

Fast program to program verify method

Fast program to program verify method

Fast program to program verify method

Control gate decoder for twin MONOS memory with two bit erase capab...

Bit line decoding scheme and circuit for dual bit memory with a dua...

Twin NAND device structure, array operations and fabrication method

Twin MONOS array metal bit organization and single cell operation