Tomonobu Noda

Person

Yokohama-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor substrate, substrate inspection method, semiconductor...
- Patent number 7,973,281
- Issue date Jul 5, 2011
- Kabushiki Kaisha Toshiba
- Hiroyuki Hayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor substrate, substrate inspection method, semiconductor...
- Patent number 7,573,066
- Issue date Aug 11, 2009
- Kabushiki Kaisha Toshiba
- Hiroyuki Hayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for monitoring manufacturing apparatuses
- Patent number 7,221,991
- Issue date May 22, 2007
- Kabushiki Kaisha Toshiba
- Hiroshi Matsushita
- G01 - MEASURING TESTING
Information Patent Grant
System for and method of evaluating mask patterns
- Patent number 6,711,733
- Issue date Mar 23, 2004
- Kabushiki Kaisha Toshiba
- Tomonobu Noda
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Manufacturing process evaluation method for semiconductor device an...
- Patent number 6,671,861
- Issue date Dec 30, 2003
- Kabushiki Kaisha Toshiba
- Tomonobu Noda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of evaluating critical locations on a semiconductor apparatu...
- Patent number 6,657,735
- Issue date Dec 2, 2003
- Kabushiki Kaisha Toshiba
- Tomonobu Noda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulated defective wafer and pattern defect inspection recipe prep...
- Patent number 6,583,870
- Issue date Jun 24, 2003
- Kabushiki Kaisha Toshiba
- Tomonobu Noda
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor substrate, substrate inspection method, semiconductor...
- Publication number 20090272901
- Publication date Nov 5, 2009
- Kabushiki Kaisha Toshiba
- Hiroyuki Hayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor substrate, substrate inspection method, semiconductor...
- Publication number 20080011947
- Publication date Jan 17, 2008
- Hiroyuki Hayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for controlling manufacturing apparatuses
- Publication number 20050194590
- Publication date Sep 8, 2005
- Hiroshi Matsushita
- G05 - CONTROLLING REGULATING
Information Patent Application
System for and method of evaluating mask patterns
- Publication number 20030056184
- Publication date Mar 20, 2003
- Kabushiki Kaisha Toshiba
- Tomonobu Noda
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Manufacturing process evaluation method for semiconductor device an...
- Publication number 20020144221
- Publication date Oct 3, 2002
- Tomonobu Noda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of evaluating critical locations on a semiconductor apparatu...
- Publication number 20020030187
- Publication date Mar 14, 2002
- Tomonobu Noda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Simulated defective wafer and pattern defect inspection recipe prep...
- Publication number 20020006497
- Publication date Jan 17, 2002
- KABUSHIKI KAISHA TOSHIBA
- Tomonobu Noda
- H01 - BASIC ELECTRIC ELEMENTS

Tomonobu Noda

Person

Patents Grantslast 30 patents

Semiconductor substrate, substrate inspection method, semiconductor...

Semiconductor substrate, substrate inspection method, semiconductor...

System and method for monitoring manufacturing apparatuses

System for and method of evaluating mask patterns

Manufacturing process evaluation method for semiconductor device an...

Method of evaluating critical locations on a semiconductor apparatu...

Simulated defective wafer and pattern defect inspection recipe prep...

Patents Applicationslast 30 patents

Semiconductor substrate, substrate inspection method, semiconductor...

Semiconductor substrate, substrate inspection method, semiconductor...

System and method for controlling manufacturing apparatuses

System for and method of evaluating mask patterns

Manufacturing process evaluation method for semiconductor device an...

Method of evaluating critical locations on a semiconductor apparatu...

Simulated defective wafer and pattern defect inspection recipe prep...