Tong Liu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Increased deposition efficiency and higher chamber conductance with...
- Patent number 9,023,227
- Issue date May 5, 2015
- Applied Materials, Inc.
- Jivko Dinev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser scribing and plasma etch for high die break strength and clea...
- Patent number 8,993,414
- Issue date Mar 31, 2015
- Applied Materials, Inc.
- Brad Eaton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for etching through-silicon vias with tunable profile angles
- Patent number 8,987,140
- Issue date Mar 24, 2015
- Applied Materials, Inc.
- Puneet Bajaj
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 7,426,665
- Issue date Sep 16, 2008
- Actel Corporation
- Jung-Cheun Lien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 7,342,416
- Issue date Mar 11, 2008
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 7,157,938
- Issue date Jan 2, 2007
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Freeway routing system for a gate array
- Patent number 7,137,095
- Issue date Nov 14, 2006
- Actel Corporation
- Tong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-tile buffer system for a field programmable gate array
- Patent number 7,132,853
- Issue date Nov 7, 2006
- Actel Corporation
- Sheng Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-tile buffer system for a field programmable gate array
- Patent number 7,053,653
- Issue date May 30, 2006
- Actel Corporation
- Sheng Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 7,015,719
- Issue date Mar 21, 2006
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,888,375
- Issue date May 3, 2005
- Actel Corporation
- Sheng Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,870,396
- Issue date Mar 22, 2005
- Actel Corporation
- Jung-Cheun Lien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Inter-tile buffer system for a field programmable gate array
- Patent number 6,800,884
- Issue date Oct 5, 2004
- Actel Corporation
- Sheng Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-programmable gate array architecture
- Patent number 6,774,672
- Issue date Aug 10, 2004
- Actel Corporation
- Jung-Cheun Lien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable gate array freeway architecture
- Patent number 6,774,669
- Issue date Aug 10, 2004
- Actel Corporation
- Tong Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Intra-tile buffer system for a field programmable gate array
- Patent number 6,774,670
- Issue date Aug 10, 2004
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,744,278
- Issue date Jun 1, 2004
- Actel Corporation
- Tong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing structures for a tileable field-programmable gate array arc...
- Patent number 6,731,133
- Issue date May 4, 2004
- Actel Corporation
- Sheng Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,700,404
- Issue date Mar 2, 2004
- Actel Corporation
- Sheng Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,611,153
- Issue date Aug 26, 2003
- Actel Corporation
- Jung-Cheun Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tileable field-programmable gate array architecture
- Patent number 6,476,636
- Issue date Nov 5, 2002
- Actel Corporation
- Jung-Cheun Lien
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
3D DRAM Access Transistor
- Publication number 20240373622
- Publication date Nov 7, 2024
- Applied Materials, Inc.
- Tong Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT
- Publication number 20240341090
- Publication date Oct 10, 2024
- Applied Materials, Inc.
- Sony VARGHESE
Information Patent Application
MEMORY DEVICES AND METHODS OF FORMING THE SAME
- Publication number 20240334683
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Tong Liu
Information Patent Application
METHOD FOR ETCHING HIGH ASPECT RATIO STRUCTURES
- Publication number 20240332031
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Feng QIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEA...
- Publication number 20150200119
- Publication date Jul 16, 2015
- Brad EATON
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND SMOO...
- Publication number 20150011073
- Publication date Jan 8, 2015
- Wei-Sheng Lei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ETCHING A SUBSTRATE
- Publication number 20140335679
- Publication date Nov 13, 2014
- TONG LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEA...
- Publication number 20140017881
- Publication date Jan 16, 2014
- Brad EATON
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
INCREASED DEPOSITION EFFICIENCY AND HIGHER CHAMBER CONDUCTANCE WITH...
- Publication number 20130005152
- Publication date Jan 3, 2013
- Applied Materials, Inc.
- JIVKO DINEV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES
- Publication number 20120270404
- Publication date Oct 25, 2012
- Applied Materials, Inc.
- Puneet Bajaj
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE
- Publication number 20080238477
- Publication date Oct 2, 2008
- Actel Corporation
- Sheng Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FREEWAY ROUTING SYSTEM FOR A GATE ARRAY
- Publication number 20070089082
- Publication date Apr 19, 2007
- Actel Corporation
- Tong Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE
- Publication number 20070075742
- Publication date Apr 5, 2007
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Inter-tile buffer system for a field programmable gate array
- Publication number 20060186920
- Publication date Aug 24, 2006
- Actel Corporation, a California Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Tileable field-programmable gate array architecture
- Publication number 20060114024
- Publication date Jun 1, 2006
- Actel Corporation
- Sheng Feng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Tileable field-programmable gate array architecture
- Publication number 20030218479
- Publication date Nov 27, 2003
- Actel Corporation, a California Corporation
- Sheng Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tileable field-programmable gate array architecture
- Publication number 20030201795
- Publication date Oct 30, 2003
- Jung-Cheun Lien
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Increased deposition efficiency and higher chamber conductance with...

Laser scribing and plasma etch for high die break strength and clea...

Methods for etching through-silicon vias with tunable profile angles

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Freeway routing system for a gate array

Inter-tile buffer system for a field programmable gate array

Inter-tile buffer system for a field programmable gate array

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Inter-tile buffer system for a field programmable gate array

Field-programmable gate array architecture

Field programmable gate array freeway architecture

Intra-tile buffer system for a field programmable gate array

Tileable field-programmable gate array architecture

Routing structures for a tileable field-programmable gate array arc...

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Patents Applicationslast 30 patents

3D DRAM Access Transistor

DYNAMIC RANDOM ACCESS MEMORY (DRAM) STORAGE NODE CONTACT

MEMORY DEVICES AND METHODS OF FORMING THE SAME

METHOD FOR ETCHING HIGH ASPECT RATIO STRUCTURES

LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEA...

LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND SMOO...

METHODS FOR ETCHING A SUBSTRATE

LASER SCRIBING AND PLASMA ETCH FOR HIGH DIE BREAK STRENGTH AND CLEA...

INCREASED DEPOSITION EFFICIENCY AND HIGHER CHAMBER CONDUCTANCE WITH...

METHODS FOR ETCHING THROUGH-SILICON VIAS WITH TUNABLE PROFILE ANGLES

TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE

FREEWAY ROUTING SYSTEM FOR A GATE ARRAY

TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE

Inter-tile buffer system for a field programmable gate array

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture