Tonia G. Morris

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Training for chip select signal read operations by memory devices
- Patent number 12,009,023
- Issue date Jun 11, 2024
- Intel Corporation
- Zhenglong Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for managing thermal behavior in multichip pa...
- Patent number 11,658,159
- Issue date May 23, 2023
- Intel Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method to generate link training signals
- Patent number 11,435,909
- Issue date Sep 6, 2022
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Registering clock driver controlled decision feedback equalizer tra...
- Patent number 11,360,874
- Issue date Jun 14, 2022
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for managing thermal behavior in multichip pa...
- Patent number 11,164,847
- Issue date Nov 2, 2021
- Intel Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 11,061,590
- Issue date Jul 13, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enumerated per device addressability for memory subsystems
- Patent number 10,997,096
- Issue date May 4, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus MR register programming process
- Patent number 10,891,243
- Issue date Jan 12, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controller apparatus, host controller device, and method for a...
- Patent number 10,635,628
- Issue date Apr 28, 2020
- Intel Corporation
- Christina Jue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 10,482,041
- Issue date Nov 19, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 10,416,912
- Issue date Sep 17, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus MR register programming process
- Patent number 10,380,043
- Issue date Aug 13, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 10,331,585
- Issue date Jun 25, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal phase optimization in memory interface training
- Patent number 10,148,416
- Issue date Dec 4, 2018
- Intel Corporation
- Tonia G Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Read training a memory controller
- Patent number 9,766,817
- Issue date Sep 19, 2017
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,627,029
- Issue date Apr 18, 2017
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Read training a memory controller
- Patent number 9,495,103
- Issue date Nov 15, 2016
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 9,058,111
- Issue date Jun 16, 2015
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,025,399
- Issue date May 5, 2015
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Read training a memory controller
- Patent number 9,021,154
- Issue date Apr 28, 2015
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic physical memory replacement through address swapping
- Patent number 8,495,435
- Issue date Jul 23, 2013
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for context enabled search
- Patent number 7,289,806
- Issue date Oct 30, 2007
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Imager having multiple storage locations for each pixel sensor
- Patent number 7,098,952
- Issue date Aug 29, 2006
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for high-speed broadband illuminant discrimina...
- Patent number 6,992,709
- Issue date Jan 31, 2006
- Intel Corporation
- Kannan Raj
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for processing a photocurrent in both discrete...
- Patent number 6,741,282
- Issue date May 25, 2004
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Imaging system having multiple image capture modes
- Patent number 6,697,112
- Issue date Feb 24, 2004
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Controlling integration times of pixel sensors
- Patent number 6,665,010
- Issue date Dec 16, 2003
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pre-subtracting architecture for enabling multiple spectrum image s...
- Patent number 6,657,663
- Issue date Dec 2, 2003
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for providing a single-instruction multiple da...
- Patent number 6,573,936
- Issue date Jun 3, 2003
- Intel Corporation
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Application of personality models and interaction with synthetic ch...
- Patent number 6,526,395
- Issue date Feb 25, 2003
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES
- Publication number 20220148639
- Publication date May 12, 2022
- Intel Corporation
- Zhenglong WU
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP PA...
- Publication number 20220013505
- Publication date Jan 13, 2022
- Intel Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO PROCESS DATA PACKETS FOR LOGICAL AND VIRTU...
- Publication number 20210149707
- Publication date May 20, 2021
- Intel Corporation
- Akhilesh Thyagaturu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRA...
- Publication number 20200334121
- Publication date Oct 22, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL
- Publication number 20200110551
- Publication date Apr 9, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP P...
- Publication number 20200105722
- Publication date Apr 2, 2020
- Intel Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20200065266
- Publication date Feb 27, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, SYSTEM AND METHOD TO GENERATE LINK TRAINING SIGNALS
- Publication number 20200042209
- Publication date Feb 6, 2020
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRA...
- Publication number 20190095308
- Publication date Mar 28, 2019
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20190095361
- Publication date Mar 28, 2019
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Controller Apparatus, Host Controller Device, and Method for a...
- Publication number 20190042519
- Publication date Feb 7, 2019
- Intel Corporation
- Christina Jue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS
- Publication number 20190042498
- Publication date Feb 7, 2019
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Module With Integrated Training
- Publication number 20180188959
- Publication date Jul 5, 2018
- Shachi K. Thakkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...
- Publication number 20180181504
- Publication date Jun 28, 2018
- Intel Corporation
- Tonia Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL
- Publication number 20180121123
- Publication date May 3, 2018
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL PHASE OPTIMIZATION IN MEMORY INTERFACE TRAINING
- Publication number 20180069692
- Publication date Mar 8, 2018
- Intel Corporation
- Tonia G. MORRIS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20170286330
- Publication date Oct 5, 2017
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20170031846
- Publication date Feb 2, 2017
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...
- Publication number 20150325281
- Publication date Nov 12, 2015
- Intel Corporation
- Tonia G. MORRIS
- G11 - INFORMATION STORAGE
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113234
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113215
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113235
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150095565
- Publication date Apr 2, 2015
- INTEL CORPORATION
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PHYSICAL MEMORY REPLACEMENT THROUGH ADDRESS SWAPPING
- Publication number 20120072768
- Publication date Mar 22, 2012
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual memory management system
- Publication number 20060004984
- Publication date Jan 5, 2006
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for context enabled search
- Publication number 20050223030
- Publication date Oct 6, 2005
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Imaging device with liquid crystal shutter
- Publication number 20040212724
- Publication date Oct 28, 2004
- Edward J. Bawolek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for providing a single-instruction multiple da...
- Publication number 20030189658
- Publication date Oct 9, 2003
- Tonia G. Morris
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IMAGING SYSTEM HAVING MULTIPLE IMAGE CAPTURE MODES
- Publication number 20030164884
- Publication date Sep 4, 2003
- TONIA G. MORRIS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PRE-SUBTRACTING ARCHITECTURE FOR ENABLING MULTIPLE SPECTRUM IMAGE S...
- Publication number 20030112353
- Publication date Jun 19, 2003
- TONIA G. MORRIS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Tonia G. Morris

Person

Patents Grantslast 30 patents

Training for chip select signal read operations by memory devices

Methods and apparatus for managing thermal behavior in multichip pa...

Device, system and method to generate link training signals

Registering clock driver controlled decision feedback equalizer tra...

Methods and apparatus for managing thermal behavior in multichip pa...

Efficiently training memory device chip select control

Enumerated per device addressability for memory subsystems

Memory bus MR register programming process

Host controller apparatus, host controller device, and method for a...

Read training a memory controller

Efficiently training memory device chip select control

Memory bus MR register programming process

Read training a memory controller

Signal phase optimization in memory interface training

Read training a memory controller

Method for training a control signal based on a strobe signal in a...

Read training a memory controller

Read training a memory controller

Method for training a control signal based on a strobe signal in a...

Read training a memory controller

Dynamic physical memory replacement through address swapping

Method and apparatus for context enabled search

Imager having multiple storage locations for each pixel sensor

Method and apparatus for high-speed broadband illuminant discrimina...

Method and apparatus for processing a photocurrent in both discrete...

Imaging system having multiple image capture modes

Controlling integration times of pixel sensors

Pre-subtracting architecture for enabling multiple spectrum image s...

Method and apparatus for providing a single-instruction multiple da...

Application of personality models and interaction with synthetic ch...

Patents Applicationslast 30 patents

TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES

METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP PA...

METHODS AND APPARATUS TO PROCESS DATA PACKETS FOR LOGICAL AND VIRTU...

REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRA...

EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL

METHODS AND APPARATUS FOR MANAGING THERMAL BEHAVIOR IN MULTICHIP P...

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

DEVICE, SYSTEM AND METHOD TO GENERATE LINK TRAINING SIGNALS

REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRA...

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

Host Controller Apparatus, Host Controller Device, and Method for a...

ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS

Memory Module With Integrated Training

APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...

EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL

SIGNAL PHASE OPTIMIZATION IN MEMORY INTERFACE TRAINING

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

DYNAMIC PHYSICAL MEMORY REPLACEMENT THROUGH ADDRESS SWAPPING

Virtual memory management system

Method and apparatus for context enabled search

Imaging device with liquid crystal shutter

Method and apparatus for providing a single-instruction multiple da...

IMAGING SYSTEM HAVING MULTIPLE IMAGE CAPTURE MODES

PRE-SUBTRACTING ARCHITECTURE FOR ENABLING MULTIPLE SPECTRUM IMAGE S...