Tonia M. ROSE

Person

Wendell, NC, US

People

Patents Applicationslast 30 patents

Information Patent Application
DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS...
- Publication number 20240345969
- Publication date Oct 17, 2024
- Intel Corporation
- Diyanesh Babu CHINNAKKONDA VIDYAPOORNACHARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODE REGISTER UPDATE (MRUPD) MODE
- Publication number 20240249795
- Publication date Jul 25, 2024
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
ACCELERATED DRAM (DYNAMIC RANDOM ACCESS MEMORY) TRAINING
- Publication number 20240241842
- Publication date Jul 18, 2024
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER...
- Publication number 20230385208
- Publication date Nov 30, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID SEARCH TO TRAIN MEMORY AND HIGH-SPEED INPUT/OUTPUT INTERFACES
- Publication number 20230214669
- Publication date Jul 6, 2023
- Intel Corporation
- Wenzhi WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL
- Publication number 20230136268
- Publication date May 4, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS DIMM WRITE LEVELING TRAINING
- Publication number 20230125412
- Publication date Apr 27, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DY...
- Publication number 20230017161
- Publication date Jan 19, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
AUTONOMOUS BACKSIDE CHIP SELECT (CS) AND COMMAND/ADDRESS (CA) TRAIN...
- Publication number 20220300197
- Publication date Sep 22, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING
- Publication number 20220301608
- Publication date Sep 22, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING
- Publication number 20220276958
- Publication date Sep 1, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO PERFORM CYCLIC REDUNDANCY CHECK TRAINING IN...
- Publication number 20220190844
- Publication date Jun 16, 2022
- Intel Corporation
- Tonia M. ROSE
- G06 - COMPUTING CALCULATING COUNTING

Tonia M. ROSE

Person

Patents Applicationslast 30 patents

DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS...

MODE REGISTER UPDATE (MRUPD) MODE

ACCELERATED DRAM (DYNAMIC RANDOM ACCESS MEMORY) TRAINING

ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER...

HYBRID SEARCH TO TRAIN MEMORY AND HIGH-SPEED INPUT/OUTPUT INTERFACES

AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL

AUTONOMOUS DIMM WRITE LEVELING TRAINING

METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DY...

AUTONOMOUS BACKSIDE CHIP SELECT (CS) AND COMMAND/ADDRESS (CA) TRAIN...

MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING

APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING

METHOD AND APPARATUS TO PERFORM CYCLIC REDUNDANCY CHECK TRAINING IN...