Tony Lee Werner

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Branch control memory
- Patent number 7,159,102
- Issue date Jan 2, 2007
- Renesas Technology Corp.
- Naohiko Irie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor architecture and operation for exploiting improved branch...
- Patent number 6,772,325
- Issue date Aug 3, 2004
- Hitachi, Ltd.
- Naohiko Irie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulating execution of smaller fixed-length branch/delay slot instr...
- Patent number 6,449,712
- Issue date Sep 10, 2002
- Hitachi, Ltd.
- Naohiko Irie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level instruction cache for embedded processors
- Patent number 6,397,296
- Issue date May 28, 2002
- Hitachi Ltd.
- Tony L. Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for invalidating instruction cache blocks in a pipeline p...
- Patent number 6,393,523
- Issue date May 21, 2002
- Hitachi Ltd.
- Chih-Jui Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indexing branch target instruction memory using target address gene...
- Patent number 6,389,531
- Issue date May 14, 2002
- Hitachi, Ltd.
- Naohiko Irle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized pre-fetch/preload mechanism for loading and speculative...
- Patent number 6,374,348
- Issue date Apr 16, 2002
- Hitachi, Ltd.
- Naohiko Irie
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Branch control memory
- Publication number 20040225871
- Publication date Nov 11, 2004
- Naohiko Irie
- G06 - COMPUTING CALCULATING COUNTING

Tony Lee Werner

Person

Patents Grantslast 30 patents

Branch control memory

Processor architecture and operation for exploiting improved branch...

Emulating execution of smaller fixed-length branch/delay slot instr...

Two-level instruction cache for embedded processors

Mechanism for invalidating instruction cache blocks in a pipeline p...

Indexing branch target instruction memory using target address gene...

Prioritized pre-fetch/preload mechanism for loading and speculative...

Patents Applicationslast 30 patents

Branch control memory