Torsten Partsch

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory component with input/output data rate alignment
- Patent number 12,229,435
- Issue date Feb 18, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component with programmable data-to-clock ratio
- Patent number 12,230,362
- Issue date Feb 18, 2025
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Data-buffer controller/control-signal redriver
- Patent number 12,211,583
- Issue date Jan 28, 2025
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Joint command dynamic random access memory (DRAM) apparatus and met...
- Patent number 12,135,901
- Issue date Nov 5, 2024
- RAMBUS INC.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect based address mapping for improved reliability
- Patent number 12,086,060
- Issue date Sep 10, 2024
- RAMBUS INC.
- Taeksang Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffered dynamic random access memory device
- Patent number 12,002,506
- Issue date Jun 4, 2024
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power memory control with on-demand bandwidth boost
- Patent number 11,996,164
- Issue date May 28, 2024
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with input/output data rate alignment
- Patent number 11,914,888
- Issue date Feb 27, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data destruction
- Patent number 11,900,984
- Issue date Feb 13, 2024
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Quad-channel DRAM
- Patent number 11,762,787
- Issue date Sep 19, 2023
- RAMBUS INC.
- Steven C. Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power memory with on-demand bandwidth boost
- Patent number 11,735,237
- Issue date Aug 22, 2023
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM security erase
- Patent number 11,600,316
- Issue date Mar 7, 2023
- RAMBUS INC.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with input/output data rate alignment
- Patent number 11,403,030
- Issue date Aug 2, 2022
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-chip package and interposer with signal line compression
- Patent number 9,153,508
- Issue date Oct 6, 2015
- Rambus Inc.
- Torsten Partsch
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY
- Publication number 20250028636
- Publication date Jan 23, 2025
- Rambus Inc.
- Taeksang SONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20240404571
- Publication date Dec 5, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY DEVICE WITH INTERFACE DIE
- Publication number 20240394178
- Publication date Nov 28, 2024
- Rambus Inc.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE
- Publication number 20240395315
- Publication date Nov 28, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods with Concurrent Link-Timing Calibration
- Publication number 20240385777
- Publication date Nov 21, 2024
- Rambus Inc.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH D...
- Publication number 20240345735
- Publication date Oct 17, 2024
- Rambus Inc.
- Brent Steven Haukness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20240289047
- Publication date Aug 29, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH IN...
- Publication number 20240281154
- Publication date Aug 22, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA DESTRUCTION
- Publication number 20240212739
- Publication date Jun 27, 2024
- Rambus Inc.
- Torsten PARTSCH
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING
- Publication number 20240127903
- Publication date Apr 18, 2024
- Rambus Inc.
- Thomas VOGELSANG
- G11 - INFORMATION STORAGE
Information Patent Application
QUAD-CHANNEL DRAM
- Publication number 20240028527
- Publication date Jan 25, 2024
- Rambus Inc.
- Steven C. WOO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20240021229
- Publication date Jan 18, 2024
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
ROW HAMMER MITIGATION
- Publication number 20230395118
- Publication date Dec 7, 2023
- Rambus Inc.
- Thomas VOGELSANG
- G11 - INFORMATION STORAGE
Information Patent Application
DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER
- Publication number 20230298642
- Publication date Sep 21, 2023
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
DATA DESTRUCTION
- Publication number 20230260564
- Publication date Aug 17, 2023
- Rambus Inc.
- Torsten PARTSCH
- G11 - INFORMATION STORAGE
Information Patent Application
RELIABILITY FOR DRAM DEVICE STACK
- Publication number 20230099474
- Publication date Mar 30, 2023
- Rambus Inc.
- Dongyun LEE
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY
- Publication number 20230081231
- Publication date Mar 16, 2023
- Rambus Inc.
- Taeksang SONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20230009384
- Publication date Jan 12, 2023
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE
- Publication number 20220366967
- Publication date Nov 17, 2022
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND MET...
- Publication number 20220283743
- Publication date Sep 8, 2022
- Rambus Inc.
- Torsten Partsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
- Publication number 20220199132
- Publication date Jun 23, 2022
- Rambus Inc.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
QUAD-CHANNEL DRAM
- Publication number 20220156204
- Publication date May 19, 2022
- Rambus Inc.
- Steven C. WOO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA DESTRUCTION
- Publication number 20210375354
- Publication date Dec 2, 2021
- Rambus Inc.
- Torsten PARTSCH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20190220222
- Publication date Jul 18, 2019
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION
- Publication number 20140197409
- Publication date Jul 17, 2014
- RAMBUS INC.
- Torsten Partsch
- G01 - MEASURING TESTING

Torsten Partsch

Person

Patents Grantslast 30 patents

Memory component with input/output data rate alignment

Memory component with programmable data-to-clock ratio

Data-buffer controller/control-signal redriver

Joint command dynamic random access memory (DRAM) apparatus and met...

Interconnect based address mapping for improved reliability

Buffered dynamic random access memory device

Low power memory control with on-demand bandwidth boost

Memory component with input/output data rate alignment

Data destruction

Quad-channel DRAM

Low power memory with on-demand bandwidth boost

DRAM security erase

Memory component with input/output data rate alignment

Multi-chip package and interposer with signal line compression

Patents Applicationslast 30 patents

INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST

STACKED MEMORY DEVICE WITH INTERFACE DIE

BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE

Systems and Methods with Concurrent Link-Timing Calibration

LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH D...

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH IN...

DATA DESTRUCTION

DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING

QUAD-CHANNEL DRAM

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST

ROW HAMMER MITIGATION

DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER

DATA DESTRUCTION

RELIABILITY FOR DRAM DEVICE STACK

INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE

JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND MET...

LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST

QUAD-CHANNEL DRAM

DATA DESTRUCTION

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION