Toshiaki Kirihata

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structures and methods of identifying unprogrammed bits for one-tim...
- Patent number 11,694,757
- Issue date Jul 4, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Structures and methods of identifying unprogrammed bits for one-tim...
- Patent number 11,417,407
- Issue date Aug 16, 2022
- GLOBALFOUNDRIES U.S. INC.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with read circuit for current-to-voltage slope characteristi...
- Patent number 11,380,373
- Issue date Jul 5, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Mohamed A. Nour
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge trap memory devices
- Patent number 11,367,734
- Issue date Jun 21, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Faraz Khan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Twin cell memory-based physically unclonable function
- Patent number 11,329,836
- Issue date May 10, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Authenticating a hardware chip using an intrinsic chip identifier
- Patent number 11,210,373
- Issue date Dec 28, 2021
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data dependent sense amplifier with symmetric margining
- Patent number 11,056,208
- Issue date Jul 6, 2021
- GLOBALFOUNDRIES U.S. INC.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Program and erase memory structures
- Patent number 10,685,705
- Issue date Jun 16, 2020
- GLOBALFOUNDRIES Inc.
- Faraz Khan
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 10,657,231
- Issue date May 19, 2020
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 10,613,754
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 10,503,402
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 10,262,119
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 9,886,193
- Issue date Feb 6, 2018
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,870,979
- Issue date Jan 16, 2018
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test method and structure for integrated circuits before complete m...
- Patent number 9,859,177
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,786,333
- Issue date Oct 10, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 9,690,927
- Issue date Jun 27, 2017
- International Business Machines Corporation
- Srivatsan Chellappa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual-bit 3-T high density MTPROM array
- Patent number 9,659,604
- Issue date May 23, 2017
- GLOBALFOUNDRIES Inc.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Disturb free bitcell and array
- Patent number 9,589,658
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES INC.
- Navin Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,559,040
- Issue date Jan 31, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wordline decoder circuits for embedded charge trap multi-time-progr...
- Patent number 9,503,091
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Toshiaki Kirihata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Encryption engine with twin cell memory array
- Patent number 9,497,027
- Issue date Nov 15, 2016
- GLOBALFOUNDRIES, INC.
- Xiang Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data-dependent self-biased differential sense amplifier
- Patent number 9,460,760
- Issue date Oct 4, 2016
- GlobalFoundries Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Physically unclonable fuse using a NOR type memory array
- Patent number 9,436,845
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Subramanian S. Iyer
- G11 - INFORMATION STORAGE
Information Patent Grant
Wiring structure for trench fuse component with methods of fabrication
- Patent number 9,431,339
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wiring structure for trench fuse component with methods of fabrication
- Patent number 9,431,340
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hierarchical in-memory sort engine
- Patent number 9,424,308
- Issue date Aug 23, 2016
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rebalancing in twin cell memory schemes to enable multiple writes
- Patent number 9,418,745
- Issue date Aug 16, 2016
- GLOBALFOUNDRIES Inc.
- Xiang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical in-memory sort engine
- Patent number 9,396,143
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitline circuits for embedded charge trap multi-time-programmable-r...
- Patent number 9,355,739
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Pamela Castalino
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURES AND METHODS OF IDENTIFYING UNPROGRAMMED BITS FOR ONE-TIM...
- Publication number 20220343988
- Publication date Oct 27, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Balaji JAYARAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE TRAP MEMORY DEVICES
- Publication number 20210242230
- Publication date Aug 5, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Faraz KHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20200074051
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20200042182
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM AND ERASE MEMORY STRUCTURES
- Publication number 20200035295
- Publication date Jan 30, 2020
- GLOBALFOUNDRIES INC.
- Faraz KHAN
- G11 - INFORMATION STORAGE
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20190155999
- Publication date May 23, 2019
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20180136846
- Publication date May 17, 2018
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...
- Publication number 20170256468
- Publication date Sep 7, 2017
- GLOBALFOUNDRIES INC.
- Janakiraman Viraraghavan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20170220784
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Srivatsan Chellappa
- G01 - MEASURING TESTING
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170206938
- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
- Publication number 20170162234
- Publication date Jun 8, 2017
- GLOBALFOUNDRIES INC.
- Ramesh Raghavan
- G11 - INFORMATION STORAGE
Information Patent Application
DISTURB FREE BITCELL AND ARRAY
- Publication number 20170053705
- Publication date Feb 23, 2017
- GLOBALFOUNDRIES Inc.
- Navin AGARWAL
- G11 - INFORMATION STORAGE
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20160334991
- Publication date Nov 17, 2016
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER
- Publication number 20160217832
- Publication date Jul 28, 2016
- GLOBALFOUNDRIES Inc.
- Balaji Jayaraman
- G11 - INFORMATION STORAGE
Information Patent Application
HIERARCHICAL IN-MEMORY SORT ENGINE
- Publication number 20160171045
- Publication date Jun 16, 2016
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION
- Publication number 20160163642
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIERARCHICAL IN-MEMORY SORT ENGINE
- Publication number 20160085702
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150364401
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIERARCHICAL IN-MEMORY SORT ENGINE
- Publication number 20150347592
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTION ENGINE WITH TWIN CELL MEMORY ARRAY
- Publication number 20150349967
- Publication date Dec 3, 2015
- International Business Machines Corporation
- Xiang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method For Defining A Default State of a Charge Trap Based Memory Cell
- Publication number 20150318043
- Publication date Nov 5, 2015
- International Business Machines Corporation
- Sheikh Sabiq Chishti
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY BASED ON RETENTION MODULATION
- Publication number 20150279462
- Publication date Oct 1, 2015
- International Business Machines Corporation
- Subramanian S. Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY
- Publication number 20150278551
- Publication date Oct 1, 2015
- International Business Machines Corporation
- Subramanian S. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION
- Publication number 20150235945
- Publication date Aug 20, 2015
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150187642
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20150186639
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNCLONABLE ID BASED CHIP-TO-CHIP COMMUNICATION
- Publication number 20150163211
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Srivatsan Chellappa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-READ-ONLY-MEMORY FOR H...
- Publication number 20150138891
- Publication date May 21, 2015
- International Business Machiness Corporation
- Subramanian S. Iyer
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE DECODER CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGR...
- Publication number 20150138867
- Publication date May 21, 2015
- International Business Machines Corporation
- Toshiaki Kirihata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BITLINE CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-R...
- Publication number 20150138868
- Publication date May 21, 2015
- International Business Machines Corporation
- Pamela Castalino
- G11 - INFORMATION STORAGE

Toshiaki Kirihata

Person

Patents Grantslast 30 patents

Structures and methods of identifying unprogrammed bits for one-tim...

Structures and methods of identifying unprogrammed bits for one-tim...

Memory with read circuit for current-to-voltage slope characteristi...

Charge trap memory devices

Twin cell memory-based physically unclonable function

Authenticating a hardware chip using an intrinsic chip identifier

Data dependent sense amplifier with symmetric margining

Program and erase memory structures

Providing an authenticating service of a chip

Architecture and implementation of cortical system, and fabricating...

Architecture and implementation of cortical system, and fabricating...

Providing an authenticating service of a chip

Architecture and implementation of cortical system, and fabricating...

Double-sided segmented line architecture in 3D integration

Test method and structure for integrated circuits before complete m...

Dual-bit 3-T high density MTPROM array

Providing an authenticating service of a chip

Dual-bit 3-T high density MTPROM array

Disturb free bitcell and array

Double-sided segmented line architecture in 3D integration

Wordline decoder circuits for embedded charge trap multi-time-progr...

Encryption engine with twin cell memory array

Data-dependent self-biased differential sense amplifier

Physically unclonable fuse using a NOR type memory array

Wiring structure for trench fuse component with methods of fabrication

Wiring structure for trench fuse component with methods of fabrication

Hierarchical in-memory sort engine

Rebalancing in twin cell memory schemes to enable multiple writes

Hierarchical in-memory sort engine

Bitline circuits for embedded charge trap multi-time-programmable-r...

Patents Applicationslast 30 patents

STRUCTURES AND METHODS OF IDENTIFYING UNPROGRAMMED BITS FOR ONE-TIM...

CHARGE TRAP MEMORY DEVICES

SELF-AUTHENTICATING CHIP

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

PROGRAM AND ERASE MEMORY STRUCTURES

SELF-AUTHENTICATING CHIP

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

TEST METHOD AND STRUCTURE FOR INTEGRATED CIRCUITS BEFORE COMPLETE M...

SELF-AUTHENTICATING CHIP

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY

DISTURB FREE BITCELL AND ARRAY

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER

HIERARCHICAL IN-MEMORY SORT ENGINE

WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION

HIERARCHICAL IN-MEMORY SORT ENGINE

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

HIERARCHICAL IN-MEMORY SORT ENGINE

ENCRYPTION ENGINE WITH TWIN CELL MEMORY ARRAY

Method For Defining A Default State of a Charge Trap Based Memory Cell

NON-VOLATILE MEMORY BASED ON RETENTION MODULATION

PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY

WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

SELF-AUTHENTICATING CHIP

UNCLONABLE ID BASED CHIP-TO-CHIP COMMUNICATION

EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-READ-ONLY-MEMORY FOR H...

WORDLINE DECODER CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGR...

BITLINE CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-R...