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Toshiharu Saitoh
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South Burlington, VT, US
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Patents Grants
last 30 patents
Information
Patent Grant
LSSD-compatible edge-triggered shift register latch
Patent number
7,543,203
Issue date
Jun 2, 2009
International Business Machines Corporation
Gerry Ashton
G01 - MEASURING TESTING
Information
Patent Grant
Method for testing embedded DRAM arrays
Patent number
7,237,165
Issue date
Jun 26, 2007
International Business Machines Corporation
Laura S. Chadwick
G11 - INFORMATION STORAGE
Information
Patent Grant
Testing and repair methodology for memories having redundancy
Patent number
7,222,274
Issue date
May 22, 2007
International Business Machines Corporation
Michael L. Combs
G11 - INFORMATION STORAGE
Information
Patent Grant
Method for testing embedded DRAM arrays
Patent number
7,073,100
Issue date
Jul 4, 2006
International Business Machines Corporation
Laura S. Chadwick
G11 - INFORMATION STORAGE
Information
Patent Grant
Self-timed and self-tested fuse blow
Patent number
6,819,160
Issue date
Nov 16, 2004
International Business Machines Corporation
Toshiharu Saitoh
G11 - INFORMATION STORAGE
Information
Patent Grant
Reduced-pin integrated circuit I/O test
Patent number
6,397,361
Issue date
May 28, 2002
International Business Machines Corporation
Toshiharu Saitoh
G11 - INFORMATION STORAGE
Information
Patent Grant
Low power LSSD flip flops and a flushable single clock splitter for...
Patent number
6,304,122
Issue date
Oct 16, 2001
International Business Machines Corporation
Roger P. Gregor
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Method and apparatus for testing the data output system of a memory...
Patent number
5,826,006
Issue date
Oct 20, 1998
International Business Machines Corporation
Toshiharu Saitoh
G11 - INFORMATION STORAGE
Information
Patent Grant
Method and apparatus for testing the address system of a memory system
Patent number
5,689,514
Issue date
Nov 18, 1997
International Business Machines Corporation
Toshiharu Saitoh
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
LSSD-COMPATIBLE EDGE-TRIGGERED SHIFT REGISTER LATCH
Publication number
20050204244
Publication date
Sep 15, 2005
International Business Machines Corporation
Gerry Ashton
G01 - MEASURING TESTING
Information
Patent Application
TESTING AND REPAIR METHODOLOGY FOR MEMORIES HAVING REDUNDANCY
Publication number
20050188287
Publication date
Aug 25, 2005
International Business Machines Corporation
Michael L. Combs
G01 - MEASURING TESTING
Information
Patent Application
Method for testing embedded DRAM arrays
Publication number
20050088888
Publication date
Apr 28, 2005
Laura S. Chadwick
G11 - INFORMATION STORAGE
Information
Patent Application
Self-timed and self-tested fuse blow
Publication number
20040090261
Publication date
May 13, 2004
International Business Machines Corporation
Toshiharu Saitoh
G11 - INFORMATION STORAGE
Information
Patent Application
Method for testing embedded DRAM arrays
Publication number
20040093539
Publication date
May 13, 2004
International Business Machines Corporation
Laura S. Chadwick
G11 - INFORMATION STORAGE