Toshikazu Endo

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Partition response surface modeling
- Patent number 8,572,525
- Issue date Oct 29, 2013
- Mentor Graphics Corporation
- Marko P Chew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite wire indexing for programmable logic devices
- Patent number 8,286,116
- Issue date Oct 9, 2012
- Lattice Semiconductor Corporation
- Toshikazu Endo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wire mapping for programmable logic devices
- Patent number 8,104,009
- Issue date Jan 24, 2012
- Lattice Semiconductor Corporation
- Byung-Kyoo Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wire mapping for programmable logic devices
- Patent number 7,890,913
- Issue date Feb 15, 2011
- Lattice Semiconductor Corporation
- Byung-Kyoo Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Composite wire indexing for programmable logic devices
- Patent number 7,788,623
- Issue date Aug 31, 2010
- Lattice Semiconductor Corporation
- Toshikazu Endo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Controllable Turn-Around Time For Post Tape-Out Flow
- Publication number 20140040848
- Publication date Feb 6, 2014
- Mentor Graphics Corporation
- Toshikazu Endo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partition Response Surface Modeling
- Publication number 20110047520
- Publication date Feb 24, 2011
- Mentor Graphics Corporation
- Marko P Chew
- G06 - COMPUTING CALCULATING COUNTING