Toshio Yamamura

Person

Yokohama-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 11,295,823
- Issue date Apr 5, 2022
- Kioxia Corporation
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 10,741,266
- Issue date Aug 11, 2020
- TOSHIBA MEMORY CORPORATION
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 10,410,731
- Issue date Sep 10, 2019
- TOSHIBA MEMORY CORPORATION
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device and memory system
- Patent number 10,026,491
- Issue date Jul 17, 2018
- TOSHIBA MEMORY CORPORATION
- Yuko Utsunomiya
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 9,870,831
- Issue date Jan 16, 2018
- TOSHIBA MEMORY CORPORATION
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 9,536,610
- Issue date Jan 3, 2017
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 8,743,625
- Issue date Jun 3, 2014
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 8,477,541
- Issue date Jul 2, 2013
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor storage device and method of reading data therefrom
- Patent number 8,320,200
- Issue date Nov 27, 2012
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 8,218,374
- Issue date Jul 10, 2012
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 8,218,373
- Issue date Jul 10, 2012
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor storage device and method of reading data therefrom
- Patent number 8,111,562
- Issue date Feb 7, 2012
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 7,916,555
- Issue date Mar 29, 2011
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor storage device having guaranteed and back...
- Patent number 7,894,262
- Issue date Feb 22, 2011
- Kabushiki Kaisha Toshiba
- Masanobu Shirakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 7,453,739
- Issue date Nov 18, 2008
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory
- Patent number 7,301,834
- Issue date Nov 27, 2007
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 7,224,621
- Issue date May 29, 2007
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 7,123,515
- Issue date Oct 17, 2006
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit adapted to output pass/fail result...
- Patent number 7,023,741
- Issue date Apr 4, 2006
- Kabushiki Kaisha Toshiba
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile semiconductor memory device and data erase controlling...
- Patent number 6,512,702
- Issue date Jan 28, 2003
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory equipped with data latch circuits...
- Patent number 6,418,052
- Issue date Jul 9, 2002
- Kabushiki Kaisha Toshiba
- Noboru Shibata
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory capable of storing one-bit data o...
- Patent number 6,331,945
- Issue date Dec 18, 2001
- Kabushiki Kaisha Toshiba
- Noboru Shibata
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory capable of storing 1-bit data or...
- Patent number 6,122,193
- Issue date Sep 19, 2000
- Kabushiki Kaisha Toshiba
- Noboru Shibata
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay circuit, oscillation circuit and semiconductor memory device
- Patent number 5,969,557
- Issue date Oct 19, 1999
- Kabushiki Kaisha Toshiba
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory device having suitable writing eff...
- Patent number 5,682,346
- Issue date Oct 28, 1997
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay circuit, oscillation circuit and semiconductor memory device
- Patent number 5,627,488
- Issue date May 6, 1997
- Kabushiki Kaisha Toshiba
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory
- Patent number 5,615,148
- Issue date Mar 25, 1997
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory device using successively longer...
- Patent number 5,436,913
- Issue date Jul 25, 1995
- Kabushiki Kaisha Toshiba
- Toshio Yamamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Block erasable nonvolatile memory device
- Patent number 5,371,702
- Issue date Dec 6, 1994
- Kabushiki Kaisha Toshiba
- Hiroto Nakai
- G11 - INFORMATION STORAGE
Information Patent Grant
Stereoscopic X-ray device
- Patent number 4,287,420
- Issue date Sep 1, 1981
- Toshiba Corporation
- Toshio Yamamura
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20200321067
- Publication date Oct 8, 2020
- Toshiba Memory Corporation
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20190362800
- Publication date Nov 28, 2019
- Toshiba Memory Corporation
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20180096729
- Publication date Apr 5, 2018
- Toshiba Memory Corporation
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
- Publication number 20180075917
- Publication date Mar 15, 2018
- Toshiba Memory Corporation
- Yuko UTSUNOMIYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20170076817
- Publication date Mar 16, 2017
- KABUSHIKI KAISHA TOSHIBA
- Hiroshi NAKAMURA
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20140226410
- Publication date Aug 14, 2014
- KABUSHIKI KAISHA TOSHIBA
- Hiroshi NAKAMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20130262754
- Publication date Oct 3, 2013
- KABUSHIKI KAISHA TOSHIBA
- Hiroshi NAKAMURA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20120243322
- Publication date Sep 27, 2012
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM
- Publication number 20120092930
- Publication date Apr 19, 2012
- Toshio YAMAMURA
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20110096606
- Publication date Apr 28, 2011
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20110090742
- Publication date Apr 21, 2011
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM
- Publication number 20090168530
- Publication date Jul 2, 2009
- Toshio YAMAMURA
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
- Publication number 20090154245
- Publication date Jun 18, 2009
- Kabushiki Kaisha Toshiba
- Masanobu SHIRAKAWA
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20090080264
- Publication date Mar 26, 2009
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...
- Publication number 20070201279
- Publication date Aug 30, 2007
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit adapted to output pass/fail result...
- Publication number 20070002635
- Publication date Jan 4, 2007
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit adapted to output pass/fail result...
- Publication number 20050190602
- Publication date Sep 1, 2005
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor memory
- Publication number 20040136245
- Publication date Jul 15, 2004
- Hiroshi Makamura
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor integrated circuit adapted to output pass/fail result...
- Publication number 20030156455
- Publication date Aug 21, 2003
- Hiroshi Nakamura
- G06 - COMPUTING CALCULATING COUNTING

Toshio Yamamura

Person

Patents Grantslast 30 patents

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor memory device and memory system

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor storage device and method of reading data therefrom

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor storage device and method of reading data therefrom

Semiconductor integrated circuit adapted to output pass/fail result...

Nonvolatile semiconductor storage device having guaranteed and back...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor memory

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Non-volatile semiconductor memory device and data erase controlling...

Nonvolatile semiconductor memory equipped with data latch circuits...

Non-volatile semiconductor memory capable of storing one-bit data o...

Non-volatile semiconductor memory capable of storing 1-bit data or...

Delay circuit, oscillation circuit and semiconductor memory device

Nonvolatile semiconductor memory device having suitable writing eff...

Delay circuit, oscillation circuit and semiconductor memory device

Nonvolatile semiconductor memory

Non-volatile semiconductor memory device using successively longer...

Block erasable nonvolatile memory device

Stereoscopic X-ray device

Patents Applicationslast 30 patents

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULT...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor integrated circuit adapted to output pass/fail result...

Semiconductor memory

Semiconductor integrated circuit adapted to output pass/fail result...