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Toshitsugu Kawashima

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  • Kanagawa, JP
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Patents Grantslast 30 patents

  • Information Patent Grant

    Delayed decision feedback sequence estimator
    • Patent number 8,116,366
    • Issue date Feb 14, 2012
    • Renesas Electronics Corporation
    • Toshitsugu Kawashima
    • H04 - ELECTRIC COMMUNICATION TECHNIQUE
  • Information Patent Grant

    PLL circuit and method of controlling the same
    • Patent number 7,920,000
    • Issue date Apr 5, 2011
    • Renesas Electronics Corporation
    • Toshitsugu Kawashima
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Demultiplexer circuit
    • Patent number 7,457,323
    • Issue date Nov 25, 2008
    • NEC Electronics Corporation
    • Toshitsugu Kawashima
    • H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

  • Information Patent Application

    PLL circuit and method of cotrolling the same
    • Publication number 20100134157
    • Publication date Jun 3, 2010
    • NEC Electronics Corporation
    • Toshitsugu Kawashima
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    Delayed decision feedback sequence estimator
    • Publication number 20090268804
    • Publication date Oct 29, 2009
    • NEC Electronics Corporation
    • Toshitsugu Kawashima
    • H04 - ELECTRIC COMMUNICATION TECHNIQUE
  • Information Patent Application

    Demultiplexer circuit
    • Publication number 20050220089
    • Publication date Oct 6, 2005
    • NEC Electronics Corporation
    • Toshitsugu Kawashima
    • H04 - ELECTRIC COMMUNICATION TECHNIQUE