Toshiyuki Nagata

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Plano, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Reduced size plate layer improves misalignments for CUB DRAM
- Patent number 6,873,001
- Issue date Mar 29, 2005
- Texas Instruments Incorporated
- Toshiyuki Nagata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures and method with bitline self-aligned to vertical connection
- Patent number 6,486,518
- Issue date Nov 26, 2002
- Texas Instruments Incorporated
- Yasuhiro Okumoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxed layout for storage nodes for dynamic random access memories
- Patent number 6,166,941
- Issue date Dec 26, 2000
- Texas Instruments Incorporated
- Hiroyuki Yoshida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric memory device having compact memory cell array
- Patent number 6,028,784
- Issue date Feb 22, 2000
- Texas Instruments Incorporated
- Kazuya Mori
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Reduced size plate layer improves misalignments in CUB DRAM
- Publication number 20050030804
- Publication date Feb 10, 2005
- Toshiyuki Nagata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structures and method with bitline self-aligned to vertical connection
- Publication number 20030068856
- Publication date Apr 10, 2003
- Yasuhiro Okumoto
- H01 - BASIC ELECTRIC ELEMENTS