Toshiyuki Sadakane

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Tokyo, JP

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Patents Grantslast 30 patents

Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 8,108,809
- Issue date Jan 31, 2012
- Renesas Electronics Corporation
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing analysis method, logic synthesis method and circuit partiti...
- Patent number 7,418,688
- Issue date Aug 26, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR CALCULATING DIFFICULTY LEVEL OF ROUTING IN NETLIST
- Publication number 20090019404
- Publication date Jan 15, 2009
- RENESAS TECHNOLOGY CORP.
- Toshiyuki SADAKANE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20080295055
- Publication date Nov 27, 2008
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Routing analysis method, logic synthesis method and circuit partiti...
- Publication number 20050246676
- Publication date Nov 3, 2005
- Renesas Technology Corp.
- Toshiyuki Sadakane
- G06 - COMPUTING CALCULATING COUNTING