Tracy J. Feist

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Fort Collins, CO, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods and structure for on-chip clock jitter testing and analysis
- Patent number 8,619,935
- Issue date Dec 31, 2013
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS
- Publication number 20140070849
- Publication date Mar 13, 2014
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR ON-CHIP CLOCK JITTER TESTING AND ANALYSIS
- Publication number 20120098571
- Publication date Apr 26, 2012
- LSI Corporation
- Douglas J. Feist
- G01 - MEASURING TESTING