Tramie Tran

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Configuration sequence for programmable logic device
- Patent number 9,722,612
- Issue date Aug 1, 2017
- Lattice Semiconductor Corporation
- Umesh Ananthiah
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION SEQUENCE FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20140108628
- Publication date Apr 17, 2014
- Umesh Ananthiah
- G01 - MEASURING TESTING