Trevor J. Bauer

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrating rows of input/output blocks with memory controllers in...
- Patent number 10,963,411
- Issue date Mar 30, 2021
- Xilinx, Inc.
- Martin L. Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regularity of fabrics in programmable logic devices
- Patent number 10,726,181
- Issue date Jul 28, 2020
- Xilinx, Inc.
- Martin L. Voogel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock network architecture
- Patent number 8,937,491
- Issue date Jan 20, 2015
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for programmable device testing in stacked die...
- Patent number 8,933,447
- Issue date Jan 13, 2015
- Xilinx, Inc.
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Grant
Programmable integrated circuit with mirrored interconnect structure
- Patent number 8,120,382
- Issue date Feb 21, 2012
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock distribution to facilitate gated clocks
- Patent number 8,058,905
- Issue date Nov 15, 2011
- Xilinx, Inc.
- Matthew H. Klein
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods of implementing and modeling interconnect lines at optional...
- Patent number 8,001,511
- Issue date Aug 16, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Formation of columnar application specific circuitry using a column...
- Patent number 7,965,102
- Issue date Jun 21, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,617,472
- Issue date Nov 10, 2009
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures and methods to avoiding hold time violations in a progra...
- Patent number 7,548,089
- Issue date Jun 16, 2009
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of providing a family of related integrated circuits of dif...
- Patent number 7,498,192
- Issue date Mar 3, 2009
- Xilinx, Inc.
- F. Erich Goetting
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Yield-enhancing methods of providing a family of scaled integrated...
- Patent number 7,491,576
- Issue date Feb 17, 2009
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of columnar application specific circuitry using a column...
- Patent number 7,478,359
- Issue date Jan 13, 2009
- Xilinx, Inc.
- Trevor J. Bauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of implementing and modeling interconnect lines at optional...
- Patent number 7,451,421
- Issue date Nov 11, 2008
- Xilinx, Inc.
- Trevor J. Bauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of providing families of integrated circuits with similar d...
- Patent number 7,402,443
- Issue date Jul 22, 2008
- Xilinx, Inc.
- Raymond C. Pang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable logic block with dedicated and selectable lookup table...
- Patent number 7,375,552
- Issue date May 20, 2008
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,353,487
- Issue date Apr 1, 2008
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-product die configurable as two or more programmable integrat...
- Patent number 7,345,507
- Issue date Mar 18, 2008
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures and methods for avoiding hold time violations in a progr...
- Patent number 7,312,631
- Issue date Dec 25, 2007
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable lookup table with dual input and output terminals in R...
- Patent number 7,265,576
- Issue date Sep 4, 2007
- Xilinx, Inc.
- Venu M. Kondapalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit providing efficient implementations...
- Patent number 7,218,139
- Issue date May 15, 2007
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable lookup table with dual input and output terminals in s...
- Patent number 7,215,138
- Issue date May 8, 2007
- Xilinx, Inc.
- Venu M. Kondapalli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having a programmable input structure with bounc...
- Patent number 7,202,698
- Issue date Apr 10, 2007
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having a programmable input structure with optio...
- Patent number 7,196,543
- Issue date Mar 27, 2007
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Large crossbar switch implemented in FPGA
- Patent number 7,057,413
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed lookup table circuits and methods for programmable logic...
- Patent number 6,956,399
- Issue date Oct 18, 2005
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structures and methods of testing interconnect structures in progra...
- Patent number 6,933,747
- Issue date Aug 23, 2005
- Xilinx, Inc.
- Trevor J. Bauer
- G01 - MEASURING TESTING
Information Patent Grant
Partial reconfiguration of a programmable logic device using an on-...
- Patent number 6,907,595
- Issue date Jun 14, 2005
- Xilinx, Inc.
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Windowing circuit for aligning data and clock signals
- Patent number 6,864,715
- Issue date Mar 8, 2005
- Xilinx, Inc.
- Trevor J. Bauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pass gate multiplexer circuit with reduced susceptibility to single...
- Patent number 6,798,270
- Issue date Sep 28, 2004
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT
- Publication number 20240313781
- Publication date Sep 19, 2024
- Xilinx, Inc.
- Brian C. GAIDE
- G01 - MEASURING TESTING
Information Patent Application
CLOCK NETWORK ARCHITECTURE
- Publication number 20140132305
- Publication date May 15, 2014
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE
- Publication number 20110215834
- Publication date Sep 8, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Partial reconfiguration of a programmable logic device using an on-...
- Publication number 20040113655
- Publication date Jun 17, 2004
- Xilinx, Inc.
- Derek R. Curd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA lookup table with high speed read decoder
- Publication number 20030071653
- Publication date Apr 17, 2003
- Xilinx, Inc.
- Richard A. Carberry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interconnect structure for a programmable logic device
- Publication number 20020008541
- Publication date Jan 24, 2002
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interconnect structure for a programmable logic device
- Publication number 20010007428
- Publication date Jul 12, 2001
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY

Trevor J. Bauer

Person

Patents Grantslast 30 patents

Integrating rows of input/output blocks with memory controllers in...

Regularity of fabrics in programmable logic devices

Clock network architecture

Method and apparatus for programmable device testing in stacked die...

Programmable integrated circuit with mirrored interconnect structure

Clock distribution to facilitate gated clocks

Methods of implementing and modeling interconnect lines at optional...

Formation of columnar application specific circuitry using a column...

Regional signal-distribution network for an integrated circuit

Structures and methods to avoiding hold time violations in a progra...

Methods of providing a family of related integrated circuits of dif...

Yield-enhancing methods of providing a family of scaled integrated...

Formation of columnar application specific circuitry using a column...

Methods of implementing and modeling interconnect lines at optional...

Methods of providing families of integrated circuits with similar d...

Programmable logic block with dedicated and selectable lookup table...

Regional signal-distribution network for an integrated circuit

Multi-product die configurable as two or more programmable integrat...

Structures and methods for avoiding hold time violations in a progr...

Programmable lookup table with dual input and output terminals in R...

Programmable integrated circuit providing efficient implementations...

Programmable lookup table with dual input and output terminals in s...

Integrated circuit having a programmable input structure with bounc...

Integrated circuit having a programmable input structure with optio...

Large crossbar switch implemented in FPGA

High-speed lookup table circuits and methods for programmable logic...

Structures and methods of testing interconnect structures in progra...

Partial reconfiguration of a programmable logic device using an on-...

Windowing circuit for aligning data and clock signals

Pass gate multiplexer circuit with reduced susceptibility to single...

Patents Applicationslast 30 patents

PROGRAMMABLE LOGIC FABRIC AS DIE TO DIE INTERCONNECT

CLOCK NETWORK ARCHITECTURE

PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE

Partial reconfiguration of a programmable logic device using an on-...

FPGA lookup table with high speed read decoder

Interconnect structure for a programmable logic device

Interconnect structure for a programmable logic device