Trung A. Diep

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache memory that supports tagless addressing
- Patent number 12,124,382
- Issue date Oct 22, 2024
- RAMBUS INC.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 11,921,642
- Issue date Mar 5, 2024
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory that supports tagless addressing
- Patent number 11,537,531
- Issue date Dec 27, 2022
- RAMBUS INC.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 11,500,781
- Issue date Nov 15, 2022
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wear leveling in a memory system
- Patent number 11,176,037
- Issue date Nov 16, 2021
- Rambus, Inc.
- Trung Am Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory that supports tagless addressing
- Patent number 10,891,241
- Issue date Jan 12, 2021
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 10,853,261
- Issue date Dec 1, 2020
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wear leveling in a memory system
- Patent number 10,515,010
- Issue date Dec 24, 2019
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory that supports tagless addressing
- Patent number 10,133,676
- Issue date Nov 20, 2018
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 10,102,140
- Issue date Oct 16, 2018
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wear leveling in a memory system
- Patent number 9,934,142
- Issue date Apr 3, 2018
- Rambus, Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process authenticated memory page encryption
- Patent number 9,734,357
- Issue date Aug 15, 2017
- Rambus Inc.
- Trung Am Diep
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatuses for addressing memory caches
- Patent number 9,569,359
- Issue date Feb 14, 2017
- Rambus Inc.
- Trung Diep
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and circuits for securing proprietary memory transactions
- Patent number 9,465,961
- Issue date Oct 11, 2016
- Rambus Inc.
- Frederick A. Ware
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Remapping memory cells based on future endurance measurements
- Patent number 9,442,838
- Issue date Sep 13, 2016
- RAMBUS INC.
- Trung Diep
- G11 - INFORMATION STORAGE
Information Patent Grant
Wear leveling in a memory system
- Patent number 9,390,025
- Issue date Jul 12, 2016
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process authenticated memory page encryption
- Patent number 9,262,342
- Issue date Feb 16, 2016
- Rambus Inc.
- Trung Am Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 9,069,605
- Issue date Jun 30, 2015
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptively time-multiplexing memory references from multiple proces...
- Patent number 8,935,489
- Issue date Jan 13, 2015
- Rambus Inc.
- Steven C. Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,887,174
- Issue date Nov 11, 2014
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 8,607,235
- Issue date Dec 10, 2013
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler-based scheduling optimization hints for user-level threads
- Patent number 8,205,200
- Issue date Jun 19, 2012
- Intel Corporation
- Shih-wei Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,010,969
- Issue date Aug 30, 2011
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to emulate user-level multithreading on an OS-sequestered...
- Patent number 7,810,083
- Issue date Oct 5, 2010
- Intel Corporation
- Gautham N. Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitration mechanism for a computer system having a unified memory...
- Patent number 6,330,646
- Issue date Dec 11, 2001
- Intel Corporation
- Steve J. Clohset
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20240273032
- Publication date Aug 15, 2024
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Memory That Supports Tagless Addressing
- Publication number 20230153251
- Publication date May 18, 2023
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20230142048
- Publication date May 11, 2023
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20210232507
- Publication date Jul 29, 2021
- Rambus Inc.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Memory That Supports Tagless Addressing
- Publication number 20210157742
- Publication date May 27, 2021
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING IN A MEMORY SYSTEM
- Publication number 20200201757
- Publication date Jun 25, 2020
- RAMBUS INC.
- Trung Am Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Addressing Memory Caches
- Publication number 20190179768
- Publication date Jun 13, 2019
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Memory That Supports Tagless Addressing
- Publication number 20190102318
- Publication date Apr 4, 2019
- RAMBUS INC.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING IN A MEMORY SYSTEM
- Publication number 20180285259
- Publication date Oct 4, 2018
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES
- Publication number 20170206168
- Publication date Jul 20, 2017
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING IN A MEMORY SYSTEM
- Publication number 20170010964
- Publication date Jan 12, 2017
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION
- Publication number 20160188911
- Publication date Jun 30, 2016
- RAMBUS INC.
- Trung Am Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wear Leveling in a Memory System
- Publication number 20140372707
- Publication date Dec 18, 2014
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION
- Publication number 20140237261
- Publication date Aug 21, 2014
- RAMBUS INC.
- Trung Am Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Circuits for Securing Proprietary Memory Transactions
- Publication number 20140173238
- Publication date Jun 19, 2014
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Remapping Memory Cells Based on Future Endurance Measurements
- Publication number 20140115296
- Publication date Apr 24, 2014
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...
- Publication number 20140115594
- Publication date Apr 24, 2014
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES
- Publication number 20130332668
- Publication date Dec 12, 2013
- RAMBUS INC.
- Trung Diep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Memory That Supports Tagless Addressing
- Publication number 20130111132
- Publication date May 2, 2013
- RAMBUS INC.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVELY TIME-MULTIPLEXING MEMORY REFERENCES FROM MULTIPLE PROCES...
- Publication number 20120278583
- Publication date Nov 1, 2012
- RAMBUS INC.
- Steven C. Woo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Monitoring Instruction Set Based Thread Execution on...
- Publication number 20120017221
- Publication date Jan 19, 2012
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler-based scheduling optimization hints for user-level threads
- Publication number 20070124732
- Publication date May 31, 2007
- Shih-wei Lia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling optimizations for user-level threads
- Publication number 20070074217
- Publication date Mar 29, 2007
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for monitoring instruction set based thread execution on...
- Publication number 20060282839
- Publication date Dec 14, 2006
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to emulate user-level multithreading on an OS-sequestered...
- Publication number 20060150183
- Publication date Jul 6, 2006
- Gautham N. Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to schedule threads on OS-sequestered sequencers without...
- Publication number 20060150184
- Publication date Jul 6, 2006
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for variable pop hardware return address stack
- Publication number 20040049666
- Publication date Mar 11, 2004
- Murali M. Annavaram
- G06 - COMPUTING CALCULATING COUNTING

Trung A. Diep

Person

Patents Grantslast 30 patents

Cache memory that supports tagless addressing

Methods and apparatuses for addressing memory caches

Cache memory that supports tagless addressing

Methods and apparatuses for addressing memory caches

Wear leveling in a memory system

Cache memory that supports tagless addressing

Methods and apparatuses for addressing memory caches

Wear leveling in a memory system

Cache memory that supports tagless addressing

Methods and apparatuses for addressing memory caches

Wear leveling in a memory system

Process authenticated memory page encryption

Methods and apparatuses for addressing memory caches

Methods and circuits for securing proprietary memory transactions

Remapping memory cells based on future endurance measurements

Wear leveling in a memory system

Process authenticated memory page encryption

Mechanism to schedule threads on OS-sequestered sequencers without...

Adaptively time-multiplexing memory references from multiple proces...

Mechanism for monitoring instruction set based thread execution on...

Mechanism to schedule threads on OS-sequestered sequencers without...

Compiler-based scheduling optimization hints for user-level threads

Mechanism for monitoring instruction set based thread execution on...

Mechanism to emulate user-level multithreading on an OS-sequestered...

Arbitration mechanism for a computer system having a unified memory...

Patents Applicationslast 30 patents

Methods and Apparatuses for Addressing Memory Caches

Cache Memory That Supports Tagless Addressing

Methods and Apparatuses for Addressing Memory Caches

Methods and Apparatuses for Addressing Memory Caches

Cache Memory That Supports Tagless Addressing

WEAR LEVELING IN A MEMORY SYSTEM

Methods and Apparatuses for Addressing Memory Caches

Cache Memory That Supports Tagless Addressing

WEAR LEVELING IN A MEMORY SYSTEM

METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES

WEAR LEVELING IN A MEMORY SYSTEM

PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION

Wear Leveling in a Memory System

PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION

Methods and Circuits for Securing Proprietary Memory Transactions

Remapping Memory Cells Based on Future Endurance Measurements

MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...

METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES

Cache Memory That Supports Tagless Addressing

ADAPTIVELY TIME-MULTIPLEXING MEMORY REFERENCES FROM MULTIPLE PROCES...

Mechanism for Monitoring Instruction Set Based Thread Execution on...

Compiler-based scheduling optimization hints for user-level threads

Scheduling optimizations for user-level threads

Mechanism for monitoring instruction set based thread execution on...

Mechanism to emulate user-level multithreading on an OS-sequestered...

Mechanism to schedule threads on OS-sequestered sequencers without...

Method and apparatus for variable pop hardware return address stack