Tse-Yu Yeh

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,566,528
- Issue date Oct 22, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,352,685
- Issue date Jan 8, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replay reduction for power saving
- Patent number 8,255,670
- Issue date Aug 28, 2012
- Apple Inc.
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L1 flush mechanism to flush cache for power down and handle coheren...
- Patent number 8,171,326
- Issue date May 1, 2012
- Apple Inc.
- James B. Keller
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Misalignment predictor
- Patent number 8,171,240
- Issue date May 1, 2012
- Apple Inc.
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Misalignment predictor
- Patent number 8,117,404
- Issue date Feb 14, 2012
- Apple Inc.
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient encoding for detecting load dependency on store with misa...
- Patent number 7,996,646
- Issue date Aug 9, 2011
- Apple Inc.
- Tse-yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L1 cache flush when processor is entering low power mode
- Patent number 7,752,474
- Issue date Jul 6, 2010
- Apple Inc.
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient encoding for detecting load dependency on store with misa...
- Patent number 7,721,066
- Issue date May 18, 2010
- Apple Inc.
- Tse-yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replay reduction for power saving
- Patent number 7,647,518
- Issue date Jan 12, 2010
- Apple Inc.
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined buffer for snoop, store merging, load miss, and writeback...
- Patent number 7,398,361
- Issue date Jul 8, 2008
- P.A. Semi, Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inhibiting of a co-issuing instruction in a processor having differ...
- Patent number 7,269,714
- Issue date Sep 11, 2007
- Broadcom Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power consumption reduction in a pipeline by stalling instruction i...
- Patent number 7,203,817
- Issue date Apr 10, 2007
- Broadcom Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for processing speculative LL and SC instructions in a pi...
- Patent number 7,162,613
- Issue date Jan 9, 2007
- Broadcom Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Limiting performance in an integrated circuit to meet export restri...
- Patent number 7,100,064
- Issue date Aug 29, 2006
- Broadcom Corporation
- Robert Rogenmoser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comparing operands of instructions against a replay scoreboard to d...
- Patent number 6,976,152
- Issue date Dec 13, 2005
- Broadcom Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for processing speclative LL and SC instructions in a pip...
- Patent number 6,877,085
- Issue date Apr 5, 2005
- Broadcom Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor having a branch predictor using speculative branch r...
- Patent number 6,871,275
- Issue date Mar 22, 2005
- Intel Corporation
- Mitchell Alexander Poplingher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicate controlled software pipelined loop processing with predic...
- Patent number 6,629,238
- Issue date Sep 30, 2003
- Intel Corporation
- Judge K. Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for processing branch operations
- Patent number 6,611,910
- Issue date Aug 26, 2003
- Idea Corporation
- Harshvardhan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for branch prediction using first and second l...
- Patent number 6,553,488
- Issue date Apr 22, 2003
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microcode upgrade and special function support by executing RISC in...
- Patent number 6,542,981
- Issue date Apr 1, 2003
- Intel Corporation
- Nazar Abbas Zaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting loop exit branches
- Patent number 6,438,682
- Issue date Aug 20, 2002
- Intel Corporation
- Dale Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor executing plural instruction sets (ISA's) with ab...
- Patent number 6,430,674
- Issue date Aug 6, 2002
- Intel Corporation
- Jignesh Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized branch predictions for strongly predicted compiler branches
- Patent number 6,427,206
- Issue date Jul 30, 2002
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for cycle accounting in microprocessors
- Patent number 6,353,805
- Issue date Mar 5, 2002
- Intel Corporation
- Achmed R. Zahir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating prediction for branches in a cluster via comparison of p...
- Patent number 6,304,960
- Issue date Oct 16, 2001
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decentralized exception processing system
- Patent number 6,282,636
- Issue date Aug 28, 2001
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Return address predictor that uses branch instructions to track a l...
- Patent number 6,253,315
- Issue date Jun 26, 2001
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for processing a cluster of instructions where the instructi...
- Patent number 6,240,510
- Issue date May 29, 2001
- Intel Corporation
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20130103906
- Publication date Apr 25, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MISALIGNMENT PREDICTOR
- Publication number 20120110392
- Publication date May 3, 2012
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20120047332
- Publication date Feb 23, 2012
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast L1 Flush Mechanism
- Publication number 20100235670
- Publication date Sep 16, 2010
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Encoding for Detecting Load Dependency on Store with Misa...
- Publication number 20100169619
- Publication date Jul 1, 2010
- Tse-yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Replay Reduction for Power Saving
- Publication number 20100064120
- Publication date Mar 11, 2010
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Encoding for Detecting Load Dependency on Store with Misa...
- Publication number 20080307173
- Publication date Dec 11, 2008
- Tse-yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Uncacheable load merging
- Publication number 20080086594
- Publication date Apr 10, 2008
- P.A. Semi, Inc.
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Replay reduction for power saving
- Publication number 20080086622
- Publication date Apr 10, 2008
- P.A. Semi, Inc.
- Po-Yung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast L1 flush mechanism
- Publication number 20080077813
- Publication date Mar 27, 2008
- P.A. Semi, Inc.
- James B. Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined buffer for snoop, store merging, load miss, and writeback...
- Publication number 20070050564
- Publication date Mar 1, 2007
- P.A. Semi, Inc.
- Ramesh Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Misalignment predictor
- Publication number 20070038847
- Publication date Feb 15, 2007
- P.A. Semi, Inc.
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for processing speculative LL and SC instructions in a pi...
- Publication number 20050154862
- Publication date Jul 14, 2005
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scoreboarding mechanism in a pipeline that includes replays and red...
- Publication number 20050149698
- Publication date Jul 7, 2005
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for processing branch operations
- Publication number 20050066153
- Publication date Mar 24, 2005
- Harshvardhan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Limiting performance in an integrated circuit to meet export restri...
- Publication number 20030225999
- Publication date Dec 4, 2003
- Robert Rogenmoser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for processing speclative LL and SC instructions in a pip...
- Publication number 20030105943
- Publication date Jun 5, 2003
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Issue and retirement mechanism in processor having different pipeli...
- Publication number 20030061465
- Publication date Mar 27, 2003
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scoreboarding mechanism in a pipeline that includes replays and red...
- Publication number 20030061467
- Publication date Mar 27, 2003
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power consumption reduction mechanism for pipeline stalls
- Publication number 20030061470
- Publication date Mar 27, 2003
- Tse-Yu Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PROCESSING BRANCH OPERATIONS
- Publication number 20020095566
- Publication date Jul 18, 2002
- HARSHVARDHAN SHARANGPANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PREDICTING LOOP EXIT BRANCHES
- Publication number 20020083310
- Publication date Jun 27, 2002
- DALE MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR BRANCH PREDICTION USING FIRST AND SECOND L...
- Publication number 20010047467
- Publication date Nov 29, 2001
- TSE-YU YEH
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Combining write buffer with dynamically adjustable flush metrics

Combining write buffer with dynamically adjustable flush metrics

Replay reduction for power saving

L1 flush mechanism to flush cache for power down and handle coheren...

Misalignment predictor

Misalignment predictor

Efficient encoding for detecting load dependency on store with misa...

L1 cache flush when processor is entering low power mode

Efficient encoding for detecting load dependency on store with misa...

Replay reduction for power saving

Combined buffer for snoop, store merging, load miss, and writeback...

Inhibiting of a co-issuing instruction in a processor having differ...

Power consumption reduction in a pipeline by stalling instruction i...

Mechanism for processing speculative LL and SC instructions in a pi...

Limiting performance in an integrated circuit to meet export restri...

Comparing operands of instructions against a replay scoreboard to d...

Mechanism for processing speclative LL and SC instructions in a pip...

Microprocessor having a branch predictor using speculative branch r...

Predicate controlled software pipelined loop processing with predic...

Method for processing branch operations

Method and apparatus for branch prediction using first and second l...

Microcode upgrade and special function support by executing RISC in...

Method and apparatus for predicting loop exit branches

Processor executing plural instruction sets (ISA&#x00027;s) with ab...

Optimized branch predictions for strongly predicted compiler branches

Apparatus and method for cycle accounting in microprocessors

Validating prediction for branches in a cluster via comparison of p...

Decentralized exception processing system

Return address predictor that uses branch instructions to track a l...

System for processing a cluster of instructions where the instructi...

Patents Applicationslast 30 patents

Combining Write Buffer with Dynamically Adjustable Flush Metrics

MISALIGNMENT PREDICTOR

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Fast L1 Flush Mechanism

Efficient Encoding for Detecting Load Dependency on Store with Misa...

Replay Reduction for Power Saving

Efficient Encoding for Detecting Load Dependency on Store with Misa...

Uncacheable load merging

Replay reduction for power saving

Fast L1 flush mechanism

Combined buffer for snoop, store merging, load miss, and writeback...

Misalignment predictor

Mechanism for processing speculative LL and SC instructions in a pi...

Scoreboarding mechanism in a pipeline that includes replays and red...

Method for processing branch operations

Limiting performance in an integrated circuit to meet export restri...

Mechanism for processing speclative LL and SC instructions in a pip...

Issue and retirement mechanism in processor having different pipeli...

Scoreboarding mechanism in a pipeline that includes replays and red...

Power consumption reduction mechanism for pipeline stalls

METHOD FOR PROCESSING BRANCH OPERATIONS

METHOD AND APPARATUS FOR PREDICTING LOOP EXIT BRANCHES

METHOD AND APPARATUS FOR BRANCH PREDICTION USING FIRST AND SECOND L...

Processor executing plural instruction sets (ISA's) with ab...