Tseng Chin Lo

Person

Hsin-Chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of measuring mask overlay using test patterns
- Patent number 12,271,116
- Issue date Apr 8, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 12,183,729
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 11,776,948
- Issue date Oct 3, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit overlay test patterns and method thereof
- Patent number 11,762,302
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 11,309,307
- Issue date Apr 19, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit overlay test patterns and method thereof
- Patent number 11,016,398
- Issue date May 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tseng Chin Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 10,679,980
- Issue date Jun 9, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 10,388,645
- Issue date Aug 20, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit filler and method thereof
- Patent number 10,283,496
- Issue date May 7, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of test probe alignment control
- Patent number 10,161,965
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Long Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multidirectional semiconductor arrangement testing
- Patent number 9,995,770
- Issue date Jun 12, 2018
- Taiwan Semiconductor Manufacturing Company Limited
- Tseng-Chin Lo
- G01 - MEASURING TESTING
Information Patent Grant
Method of test probe alignment control
- Patent number 9,000,798
- Issue date Apr 7, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Long Chen
- G01 - MEASURING TESTING
Information Patent Grant
Reverse dummy insertion algorithm
- Patent number 7,934,173
- Issue date Apr 26, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiing-Shin Shyu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Reverse dummy insertion algorithm
- Patent number 7,853,918
- Issue date Dec 14, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiing-Shin Shyu
Information Patent Grant
Test pad design for reducing the effect of contact resistances
- Patent number 7,825,678
- Issue date Nov 2, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yih-Yuh Doong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High accuracy and universal on-chip switch matrix testline
- Patent number 7,782,073
- Issue date Aug 24, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tseng Chin Lo
- G01 - MEASURING TESTING
Information Patent Grant
Electrical overlay/spacing monitor method using a ladder resistor
- Patent number 6,323,097
- Issue date Nov 27, 2001
- Taiwan Semiconductor Manufacturing Company
- Shien-Yang Wu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20230369309
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Overlay Test Patterns And Method Thereof
- Publication number 20230359131
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20220246600
- Publication date Aug 4, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Overlay Test Patterns and Method Thereof
- Publication number 20210278771
- Publication date Sep 9, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20200303366
- Publication date Sep 24, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Overlay Test Patterns and Method Thereof
- Publication number 20190384185
- Publication date Dec 19, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Tseng Chin Lo
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20190371783
- Publication date Dec 5, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20180358348
- Publication date Dec 13, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT FILLER AND METHOD THEREOF
- Publication number 20180006010
- Publication date Jan 4, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tseng Chin LO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIDIRECTIONAL SEMICONDUCTOR ARRANGEMENT TESTING
- Publication number 20150268271
- Publication date Sep 24, 2015
- Taiwan Semiconductor Manufacturing Company Limited
- Tseng-Chin Lo
- G01 - MEASURING TESTING
Information Patent Application
Method of Test Probe Alignment Control
- Publication number 20150192616
- Publication date Jul 9, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Long Chen
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF TEST PROBE ALIGNMENT CONTROL
- Publication number 20130335109
- Publication date Dec 19, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Long Chen
- G01 - MEASURING TESTING
Information Patent Application
Test Pad Design for Reducing the Effect of Contact Resistances
- Publication number 20100045325
- Publication date Feb 25, 2010
- Yih-Yuh Doong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reverse Dummy Insertion Algorithm
- Publication number 20090181314
- Publication date Jul 16, 2009
- Jiing-Shin Shyu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
High accuracy and universal on-chip switch matrix testline
- Publication number 20080238453
- Publication date Oct 2, 2008
- Tseng Chin Lo
- G01 - MEASURING TESTING
Information Patent Application
Network based integrated circuit testline generator
- Publication number 20080244475
- Publication date Oct 2, 2008
- Tseng Chin Lo
- G06 - COMPUTING CALCULATING COUNTING

Tseng Chin Lo

Person

Patents Grantslast 30 patents

Method of measuring mask overlay using test patterns

Integrated circuit filler and method thereof

Integrated circuit filler and method thereof

Integrated circuit overlay test patterns and method thereof

Integrated circuit filler and method thereof

Integrated circuit overlay test patterns and method thereof

Integrated circuit filler and method thereof

Integrated circuit filler and method thereof

Integrated circuit filler and method thereof

Method of test probe alignment control

Multidirectional semiconductor arrangement testing

Method of test probe alignment control

Reverse dummy insertion algorithm

Reverse dummy insertion algorithm

Test pad design for reducing the effect of contact resistances

High accuracy and universal on-chip switch matrix testline

Electrical overlay/spacing monitor method using a ladder resistor

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

Integrated Circuit Overlay Test Patterns And Method Thereof

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

Integrated Circuit Overlay Test Patterns and Method Thereof

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

Integrated Circuit Overlay Test Patterns and Method Thereof

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

INTEGRATED CIRCUIT FILLER AND METHOD THEREOF

MULTIDIRECTIONAL SEMICONDUCTOR ARRANGEMENT TESTING

Method of Test Probe Alignment Control

METHOD OF TEST PROBE ALIGNMENT CONTROL

Test Pad Design for Reducing the Effect of Contact Resistances

Reverse Dummy Insertion Algorithm

High accuracy and universal on-chip switch matrix testline

Network based integrated circuit testline generator