Tsu-Jae King Liu

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for achieving uniform etch depth using ion implantation and...
- Patent number 9,355,860
- Issue date May 31, 2016
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM cell utilizing a doubly gated vertical channel
- Patent number 8,686,497
- Issue date Apr 1, 2014
- The Regents of the University of California
- WookHyun Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning a single integrated circuit layer using automatically-ge...
- Patent number 8,592,109
- Issue date Nov 26, 2013
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Patterning a single integrated circuit layer using automatically-ge...
- Patent number 8,399,183
- Issue date Mar 19, 2013
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Low-temperature formation of polycrystalline semiconductor films vi...
- Patent number 8,043,943
- Issue date Oct 25, 2011
- The Regents of the University of California
- Roya Maboudian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Negative differential resistance pull up element for DRAM
- Patent number 7,995,380
- Issue date Aug 9, 2011
- Synopsys, Inc.
- Tsu-Jae King Liu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Sequential selective epitaxial growth
- Patent number 7,807,523
- Issue date Oct 5, 2010
- Synopsys, Inc.
- Tsu Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for capacitorless double-gate storage
- Patent number 7,710,771
- Issue date May 4, 2010
- The Regents of the University of California
- Charles C. Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced segmented channel MOS transistor with high-permittivity di...
- Patent number 7,605,449
- Issue date Oct 20, 2009
- Synopsys, Inc.
- Tsu Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning a single integrated circuit layer using multiple masks a...
- Patent number 7,560,201
- Issue date Jul 14, 2009
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced segmented channel MOS transistor with narrowed base regions
- Patent number 7,508,031
- Issue date Mar 24, 2009
- Synopsys, Inc.
- Tsu Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for achieving uniform etch depth using ion implantation and...
- Patent number 7,494,933
- Issue date Feb 24, 2009
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method For Achieving Uniform Etch Depth Using Ion Implantation And...
- Publication number 20160268372
- Publication date Sep 15, 2016
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterning A Single Integrated Circuit Layer Using Automatically-Ge...
- Publication number 20130171548
- Publication date Jul 4, 2013
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
DRAM CELL UTILIZING A DOUBLY GATED VERTICAL CHANNEL
- Publication number 20120161229
- Publication date Jun 28, 2012
- The Regents of the University of California
- WookHyun Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterning A Single Integrated Circuit Layer Using Automatically-Ge...
- Publication number 20100291476
- Publication date Nov 18, 2010
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
LOW-TEMPERATURE FORMATION OF POLYCRYSTALLINE SEMICONDUCTOR FILMS VI...
- Publication number 20100184276
- Publication date Jul 22, 2010
- The Regents of the University of California
- Roya Maboudian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Achieving Uniform Etch Depth Using Ion Implantation And...
- Publication number 20090114953
- Publication date May 7, 2009
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Negative Differential Resistance Pull Up Element For DRAM
- Publication number 20090039438
- Publication date Feb 12, 2009
- Synopsys, Inc.
- Tsu-Jae King Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Patterning A Single Integrated Circuit Layer Using Multiple Masks A...
- Publication number 20080280217
- Publication date Nov 13, 2008
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method For Achieving Uniform Etch Depth Using Ion Implantation And...
- Publication number 20080057712
- Publication date Mar 6, 2008
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Patterning A Single Integrated Circuit Layer Using Multiple Masks A...
- Publication number 20070275309
- Publication date Nov 29, 2007
- Synopsys, Inc.
- Tsu-Jae King Liu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Enhanced Segmented Channel MOS Transistor with Narrowed Base Regions
- Publication number 20070128782
- Publication date Jun 7, 2007
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhanced Segmented Channel MOS Transistor with Multi Layer Regions
- Publication number 20070120156
- Publication date May 31, 2007
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhanced Segmented Channel MOS Transistor with High-Permittivity Di...
- Publication number 20070122953
- Publication date May 31, 2007
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sequential Selective Epitaxial Growth
- Publication number 20070122954
- Publication date May 31, 2007
- Synopsys, Inc.
- Tsu-Jae King Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Engineered barrier layer and gate gap for transistors with negative...
- Publication number 20070120186
- Publication date May 31, 2007
- Synopsys, Inc.
- Qiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked memory cell utilizing negative differential resistance devices
- Publication number 20060125017
- Publication date Jun 15, 2006
- Synopsys, Inc.
- Tsu-Jae King Liu
- G11 - INFORMATION STORAGE

Tsu-Jae King Liu

Person

Patents Grantslast 30 patents

Method for achieving uniform etch depth using ion implantation and...

DRAM cell utilizing a doubly gated vertical channel

Patterning a single integrated circuit layer using automatically-ge...

Patterning a single integrated circuit layer using automatically-ge...

Low-temperature formation of polycrystalline semiconductor films vi...

Negative differential resistance pull up element for DRAM

Sequential selective epitaxial growth

Method and apparatus for capacitorless double-gate storage

Enhanced segmented channel MOS transistor with high-permittivity di...

Patterning a single integrated circuit layer using multiple masks a...

Enhanced segmented channel MOS transistor with narrowed base regions

Method for achieving uniform etch depth using ion implantation and...

Patents Applicationslast 30 patents

Method For Achieving Uniform Etch Depth Using Ion Implantation And...

Patterning A Single Integrated Circuit Layer Using Automatically-Ge...

DRAM CELL UTILIZING A DOUBLY GATED VERTICAL CHANNEL

Patterning A Single Integrated Circuit Layer Using Automatically-Ge...

LOW-TEMPERATURE FORMATION OF POLYCRYSTALLINE SEMICONDUCTOR FILMS VI...

Method For Achieving Uniform Etch Depth Using Ion Implantation And...

Negative Differential Resistance Pull Up Element For DRAM

Patterning A Single Integrated Circuit Layer Using Multiple Masks A...

Method For Achieving Uniform Etch Depth Using Ion Implantation And...

Patterning A Single Integrated Circuit Layer Using Multiple Masks A...

Enhanced Segmented Channel MOS Transistor with Narrowed Base Regions

Enhanced Segmented Channel MOS Transistor with Multi Layer Regions

Enhanced Segmented Channel MOS Transistor with High-Permittivity Di...

Sequential Selective Epitaxial Growth

Engineered barrier layer and gate gap for transistors with negative...

Stacked memory cell utilizing negative differential resistance devices