Tsukasa Shirotori

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Patents Grantslast 30 patents

Information Patent Grant
LSI layout design apparatus, layout design method, recording medium...
- Patent number 6,578,179
- Issue date Jun 10, 2003
- Kabushiki Kaisha Toshiba
- Tsukasa Shirotori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system having high and low speed and power consumption...
- Patent number 5,920,888
- Issue date Jul 6, 1999
- Kabushiki Kaisha Toshiba
- Tsukasa Shirotori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system with reduced tag memory power consumption
- Patent number 5,845,309
- Issue date Dec 1, 1998
- Kabushiki Kaisha Toshiba
- Tsukasa Shirotori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device employing sense amplifier control circu...
- Patent number 5,479,374
- Issue date Dec 26, 1995
- Kabushiki Kaisha Toshiba
- Tsuguo Kobayashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit capable of testing memory blocks
- Patent number 5,388,104
- Issue date Feb 7, 1995
- Kabushiki Kaisha Toshiba
- Tsukasa Shirotori
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LSI layout design apparatus, layout design method, recording medium...
- Publication number 20020042905
- Publication date Apr 11, 2002
- Tsukasa Shirotori
- G06 - COMPUTING CALCULATING COUNTING