Tuhin Mahmud

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit development using machine learning-based predict...
- Patent number 11,775,720
- Issue date Oct 3, 2023
- International Business Machines Corporation
- Tuhin Mahmud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clustering simulation failures for triage and debugging
- Patent number 11,205,092
- Issue date Dec 21, 2021
- International Business Machines Corporation
- Bryan G. Hickerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of wire tag lists for a metal stack
- Patent number 9,092,591
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis optimization with fast metric check
- Patent number 8,881,089
- Issue date Nov 4, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of wire tag lists for a metal stack
- Patent number 8,769,468
- Issue date Jul 1, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resolving global coupling timing and slew violations for buffer-dom...
- Patent number 8,365,120
- Issue date Jan 29, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent buffering and layer assignment in integrated circuit layout
- Patent number 7,895,557
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slew constrained minimum cost buffering
- Patent number 7,890,905
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer insertion to reduce wirelength in VLSI circuits
- Patent number 7,484,199
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slew constrained minimum cost buffering
- Patent number 7,448,007
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DEVELOPMENT USING MACHINE LEARNING-BASED PREDICT...
- Publication number 20230004701
- Publication date Jan 5, 2023
- International Business Machines Corporation
- Tuhin Mahmud
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLUSTERING SIMULATION FAILURES FOR TRIAGE AND DEBUGGING
- Publication number 20200327364
- Publication date Oct 15, 2020
- International Business Machines Corporation
- Bryan G. Hickerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140223397
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140195998
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resolving Global Coupling Timing and Slew Violations for Buffer-Dom...
- Publication number 20120144358
- Publication date Jun 7, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Concurrent Buffering and Layer Assignment in...
- Publication number 20090259980
- Publication date Oct 15, 2009
- Charles J. ALPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS
- Publication number 20090064080
- Publication date Mar 5, 2009
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS
- Publication number 20090013299
- Publication date Jan 8, 2009
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLEW CONSTRAINED MINIMUM COST BUFFERING
- Publication number 20080295051
- Publication date Nov 27, 2008
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Slew Constrained Minimum Cost Buffering
- Publication number 20080016479
- Publication date Jan 17, 2008
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method of Eliminating Electrical Violations
- Publication number 20070283301
- Publication date Dec 6, 2007
- Arvind K. Karandikar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Insertion to Reduce Wirelength in VLSI Circuits
- Publication number 20070271543
- Publication date Nov 22, 2007
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Tuhin Mahmud

Person

Patents Grantslast 30 patents

Integrated circuit development using machine learning-based predict...

Clustering simulation failures for triage and debugging

Automatic generation of wire tag lists for a metal stack

Physical synthesis optimization with fast metric check

Automatic generation of wire tag lists for a metal stack

Resolving global coupling timing and slew violations for buffer-dom...

Concurrent buffering and layer assignment in integrated circuit layout

Slew constrained minimum cost buffering

Buffer insertion to reduce wirelength in VLSI circuits

Slew constrained minimum cost buffering

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DEVELOPMENT USING MACHINE LEARNING-BASED PREDICT...

CLUSTERING SIMULATION FAILURES FOR TRIAGE AND DEBUGGING

Automatic Generation of Wire Tag Lists for a Metal Stack

Automatic Generation of Wire Tag Lists for a Metal Stack

Resolving Global Coupling Timing and Slew Violations for Buffer-Dom...

Method and System for Concurrent Buffering and Layer Assignment in...

BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS

BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS

SLEW CONSTRAINED MINIMUM COST BUFFERING

Slew Constrained Minimum Cost Buffering

System and Method of Eliminating Electrical Violations

Buffer Insertion to Reduce Wirelength in VLSI Circuits