Tz-Jun Kuo

Person

Zhudong Township, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming metal interconnection
- Patent number 11,715,689
- Issue date Aug 1, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via structure and methods for forming the same
- Patent number 11,551,967
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Pei Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure without barrier layer on bottom surface of via
- Patent number 11,322,391
- Issue date May 3, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tz-Jun Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming metal interconnection
- Patent number 10,714,424
- Issue date Jul 14, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure without barrier layer on bottom surface of via
- Patent number 10,453,740
- Issue date Oct 22, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Tz-Jun Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming metal interconnection
- Patent number 10,163,786
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming metal interconnection
- Patent number 9,972,529
- Issue date May 15, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an interconnection
- Patent number 9,842,767
- Issue date Dec 12, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for via plating with seed layer
- Patent number 9,640,431
- Issue date May 2, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Method of forming metal interconnection
- Patent number 9,613,856
- Issue date Apr 4, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back end of the line (BEOL) interconnect scheme
- Patent number 9,343,356
- Issue date May 17, 2016
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chi-Liang Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for via plating with seed layer
- Patent number 9,324,608
- Issue date Apr 26, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for via plating with seed layer
- Patent number 9,054,163
- Issue date Jun 9, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of semiconductor integrated circuit fabrication
- Patent number 8,749,060
- Issue date Jun 10, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming Han Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
VIA STRUCTURE AND METHODS FOR FORMING THE SAME
- Publication number 20220352012
- Publication date Nov 3, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Pei Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect Structure without Barrier Layer on Bottom Surface of Via
- Publication number 20220262675
- Publication date Aug 18, 2022
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Tz-Jun Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA STRUCTURE AND METHODS FOR FORMING THE SAME
- Publication number 20210366765
- Publication date Nov 25, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Meng-Pei Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Metal Interconnection
- Publication number 20200343177
- Publication date Oct 29, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA
- Publication number 20200035546
- Publication date Jan 30, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tz-Jun KUO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Metal Interconnection
- Publication number 20190115297
- Publication date Apr 18, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA
- Publication number 20190006230
- Publication date Jan 3, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tz-Jun KUO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Via Plating with Seed Layer
- Publication number 20170236750
- Publication date Aug 17, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Method of Forming Metal Interconnection
- Publication number 20170186685
- Publication date Jun 29, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Metal Interconnection
- Publication number 20170092536
- Publication date Mar 30, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Metal Interconnection
- Publication number 20170084483
- Publication date Mar 23, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Via Plating with Seed Layer
- Publication number 20160240434
- Publication date Aug 18, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Via Plating with Seed Layer
- Publication number 20150255334
- Publication date Sep 10, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Via Plating with Seed Layer
- Publication number 20150126030
- Publication date May 7, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Yi Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
- Publication number 20150017799
- Publication date Jan 15, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Back End of the Line (BEOL) Interconnect Scheme
- Publication number 20140231998
- Publication date Aug 21, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Chi-Liang Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
- Publication number 20140084469
- Publication date Mar 27, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming Han Lee
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Method of forming metal interconnection

Via structure and methods for forming the same

Interconnect structure without barrier layer on bottom surface of via

Method of forming metal interconnection

Interconnect structure without barrier layer on bottom surface of via

Method of forming metal interconnection

Method of forming metal interconnection

Method of forming an interconnection

Method for via plating with seed layer

Method of forming metal interconnection

Back end of the line (BEOL) interconnect scheme

Method for via plating with seed layer

Method for via plating with seed layer

Method of semiconductor integrated circuit fabrication

Patents Applicationslast 30 patents

VIA STRUCTURE AND METHODS FOR FORMING THE SAME

Interconnect Structure without Barrier Layer on Bottom Surface of Via

VIA STRUCTURE AND METHODS FOR FORMING THE SAME

Method of Forming Metal Interconnection

INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA

Method of Forming Metal Interconnection

INTERCONNECT STRUCTURE WITHOUT BARRIER LAYER ON BOTTOM SURFACE OF VIA

Method for Via Plating with Seed Layer

Method of Forming Metal Interconnection

Method of Forming Metal Interconnection

Method of Forming Metal Interconnection

Method for Via Plating with Seed Layer

Method for Via Plating with Seed Layer

Method for Via Plating with Seed Layer

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION

Back End of the Line (BEOL) Interconnect Scheme

METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION