Tzach Zemer

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic interface circuit to reduce power consumption
- Patent number 12,265,438
- Issue date Apr 1, 2025
- Apple Inc.
- Tzach Zemer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-to-die dynamic clock and power gating
- Patent number 12,248,350
- Issue date Mar 11, 2025
- Apple Inc.
- Dany Davidov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple independent on-chip interconnect
- Patent number 11,675,722
- Issue date Jun 13, 2023
- Apple Inc.
- Sergio Kolor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-to-die dynamic clock and power gating
- Patent number 11,592,889
- Issue date Feb 28, 2023
- Apple Inc.
- Dany Davidov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock/power-domain crossing circuit with asynchronous FIFO and inde...
- Patent number 10,048,893
- Issue date Aug 14, 2018
- Apple Inc.
- Mark Goikhman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sum of differences filter
- Patent number 10,038,425
- Issue date Jul 31, 2018
- Apple Inc.
- Tzach Zemer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power decimator
- Patent number 9,641,158
- Issue date May 2, 2017
- Apple Inc.
- Tzach Zemer
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Dynamic Interface Circuit to Reduce Power Consumption
- Publication number 20250190043
- Publication date Jun 12, 2025
- Apple Inc.
- Tzach Zemer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communication Fabric Structures for Increased Bandwidth
- Publication number 20250097166
- Publication date Mar 20, 2025
- Apple Inc.
- Sergio Kolor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamic Interface Circuit to Reduce Power Consumption
- Publication number 20240085968
- Publication date Mar 14, 2024
- Apple Inc.
- Tzach Zemer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Independent On-chip Interconnect
- Publication number 20230350828
- Publication date Nov 2, 2023
- Apple Inc.
- Sergio Kolor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Segment to Segment Network Interface
- Publication number 20230239252
- Publication date Jul 27, 2023
- Apple Inc.
- Sergio Kolor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Die-to-die Dynamic Clock and Power Gating
- Publication number 20230214350
- Publication date Jul 6, 2023
- Apple Inc.
- Dany Davidov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Die-to-die Dynamic Clock and Power Gating
- Publication number 20220365579
- Publication date Nov 17, 2022
- Apple Inc.
- Dany Davidov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Independent On-chip Interconnect
- Publication number 20220334997
- Publication date Oct 20, 2022
- Apple Inc.
- Sergio Kolor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER DECIMATOR
- Publication number 20170054433
- Publication date Feb 23, 2017
- Apple Inc.
- Tzach Zemer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK/POWER-DOMAIN CROSSING CIRCUIT WITH ASYNCHRONOUS FIFO AND INDE...
- Publication number 20160328182
- Publication date Nov 10, 2016
- Apple Inc.
- Mark Goikhman
- G06 - COMPUTING CALCULATING COUNTING

Tzach Zemer

Person

Patents Grantslast 30 patents

Dynamic interface circuit to reduce power consumption

Die-to-die dynamic clock and power gating

Multiple independent on-chip interconnect

Die-to-die dynamic clock and power gating

Clock/power-domain crossing circuit with asynchronous FIFO and inde...

Sum of differences filter

Low power decimator

Patents Applicationslast 30 patents

Dynamic Interface Circuit to Reduce Power Consumption

Communication Fabric Structures for Increased Bandwidth

Dynamic Interface Circuit to Reduce Power Consumption

Multiple Independent On-chip Interconnect

Segment to Segment Network Interface

Die-to-die Dynamic Clock and Power Gating

Die-to-die Dynamic Clock and Power Gating

Multiple Independent On-chip Interconnect

LOW POWER DECIMATOR

CLOCK/POWER-DOMAIN CROSSING CIRCUIT WITH ASYNCHRONOUS FIFO AND INDE...