Tze Sin Tan

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Island Glades, MY

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for using programmable logic circuitry to test...
- Patent number 9,874,607
- Issue date Jan 23, 2018
- Altera Corporation
- Chiew Khiang Kuit
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for testing multiple clock domain memories
- Patent number 9,098,486
- Issue date Aug 4, 2015
- Altera Corporation
- Tze Sin Tan
- G01 - MEASURING TESTING
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 8,189,362
- Issue date May 29, 2012
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic circuit testing with reduced overhead
- Patent number 7,996,743
- Issue date Aug 9, 2011
- Altera Corporation
- Tze Sin Tan
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for testing memory circuits
- Patent number 7,984,344
- Issue date Jul 19, 2011
- Altera Corporation
- Chin Hai Ang
- G11 - INFORMATION STORAGE
Information Patent Grant
Data encoding scheme to reduce sense current
- Patent number 7,978,493
- Issue date Jul 12, 2011
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for testing memory circuits
- Patent number 7,761,754
- Issue date Jul 20, 2010
- Altera Corporation
- Chin Hai Ang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DATA ENCODING SCHEME TO REDUCE SENSE CURRENT
- Publication number 20110292711
- Publication date Dec 1, 2011
- Jun Pin Tan
- G11 - INFORMATION STORAGE